From WikiChip
Difference between revisions of "sun microsystems/ultrasparc/stp1030bga-167"
m (Bot: moving all {{mpu}} to {{chip}}) |
|||
| (8 intermediate revisions by one other user not shown) | |||
| Line 1: | Line 1: | ||
{{sun title|UltraSPARC-I 167MHz}} | {{sun title|UltraSPARC-I 167MHz}} | ||
| − | {{ | + | {{chip |
|name=UltraSPARC-I 167MHz | |name=UltraSPARC-I 167MHz | ||
| − | |image= | + | |no image=Yes |
|designer=Sun Microsystems | |designer=Sun Microsystems | ||
|manufacturer=Texas Instruments | |manufacturer=Texas Instruments | ||
| Line 13: | Line 13: | ||
|release price=$1,395 | |release price=$1,395 | ||
|family=UltraSPARC | |family=UltraSPARC | ||
| + | |series=UltraSPARC-I | ||
|frequency=167 MHz | |frequency=167 MHz | ||
|isa=SPARC V9 | |isa=SPARC V9 | ||
|isa family=SPARC | |isa family=SPARC | ||
| − | |microarch=UltraSPARC | + | |microarch=UltraSPARC-I |
|process=0.5 µm | |process=0.5 µm | ||
|transistors=5,200,000 | |transistors=5,200,000 | ||
|technology=CMOS | |technology=CMOS | ||
| + | |die area=310 mm² | ||
|word size=64 bit | |word size=64 bit | ||
|core count=1 | |core count=1 | ||
|thread count=1 | |thread count=1 | ||
| + | |average power=28 W | ||
|v core=3.3 V | |v core=3.3 V | ||
|package module 1={{packages/sun microsystems/bga-521}} | |package module 1={{packages/sun microsystems/bga-521}} | ||
}} | }} | ||
| − | '''UltraSPARC-I | + | '''UltraSPARC-I 167MHz''' was a {{arch|64}} [[SPARC]] microprocessor designed and introduced by [[Sun Microsystems]] in late [[1995]]. This processor operates at 167 MHz and typically dissipates 28 W. |
| + | |||
| + | == Cache == | ||
| + | {{main|sun microsystems/microarchitectures/ultrasparc-i#Memory_Hierarchy|l1=UltraSPARC-I § Cache}} | ||
| + | In addition to the on-chip cache, this chip also required an external cache that is either 512 KiB, 1 MiB, 2 MiB, or 4 MiB with a line size of 64 bytes. | ||
| + | {{cache size | ||
| + | |l1 cache=32 KiB | ||
| + | |l1i cache=16 KiB | ||
| + | |l1i break=1x16 KiB | ||
| + | |l1i desc=2-way set associative | ||
| + | |l1d cache=16 KiB | ||
| + | |l1d break=1x16 KiB | ||
| + | |l1d desc=16-way set associative | ||
| + | |l1d policy=write-through | ||
| + | }} | ||
| + | |||
| + | == Documents == | ||
| + | === Datasheets === | ||
| + | * [[:File:stp1030a.pdf|UltraSPARC-I High-Performance, 167 & 200 MHz, 64-bit RISC Processor Datasheet]], October 1996 | ||
Latest revision as of 15:32, 13 December 2017
| Edit Values | ||||||
| UltraSPARC-I 167MHz | ||||||
| General Info | ||||||
| Designer | Sun Microsystems | |||||
| Manufacturer | Texas Instruments | |||||
| Model Number | UltraSPARC-I 167MHz | |||||
| Part Number | STP103OBGA-167 | |||||
| Market | Server, Workstation | |||||
| Introduction | October 2, 1995 (announced) October 2, 1995 (launched) | |||||
| Release Price | $1,395 | |||||
| General Specs | ||||||
| Family | UltraSPARC | |||||
| Series | UltraSPARC-I | |||||
| Frequency | 167 MHz | |||||
| Microarchitecture | ||||||
| ISA | SPARC V9 (SPARC) | |||||
| Microarchitecture | UltraSPARC-I | |||||
| Process | 0.5 µm | |||||
| Transistors | 5,200,000 | |||||
| Technology | CMOS | |||||
| Die | 310 mm² | |||||
| Word Size | 64 bit | |||||
| Cores | 1 | |||||
| Threads | 1 | |||||
| Electrical | ||||||
| Power dissipation (average) | 28 W | |||||
| Vcore | 3.3 V | |||||
| Packaging | ||||||
| ||||||
UltraSPARC-I 167MHz was a 64-bit SPARC microprocessor designed and introduced by Sun Microsystems in late 1995. This processor operates at 167 MHz and typically dissipates 28 W.
Cache[edit]
- Main article: UltraSPARC-I § Cache
In addition to the on-chip cache, this chip also required an external cache that is either 512 KiB, 1 MiB, 2 MiB, or 4 MiB with a line size of 64 bytes.
|
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
|||||||||||||
|
|||||||||||||
Documents[edit]
Datasheets[edit]
Facts about "UltraSPARC-I 167MHz - Sun Microsystems"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | UltraSPARC-I 167MHz - Sun Microsystems#package + |
| base frequency | 167 MHz (0.167 GHz, 167,000 kHz) + |
| core count | 1 + |
| core voltage | 3.3 V (33 dV, 330 cV, 3,300 mV) + |
| designer | Sun Microsystems + |
| die area | 310 mm² (0.481 in², 3.1 cm², 310,000,000 µm²) + |
| family | UltraSPARC + |
| first announced | October 2, 1995 + |
| first launched | October 2, 1995 + |
| full page name | sun microsystems/ultrasparc/stp1030bga-167 + |
| instance of | microprocessor + |
| isa | SPARC V9 + |
| isa family | SPARC + |
| l1$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
| l1d$ description | 16-way set associative + |
| l1d$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
| l1i$ description | 2-way set associative + |
| l1i$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
| ldate | October 2, 1995 + |
| manufacturer | Texas Instruments + |
| market segment | Server + and Workstation + |
| microarchitecture | UltraSPARC-I + |
| model number | UltraSPARC-I 167MHz + |
| name | UltraSPARC-I 167MHz + |
| package | BGA-521 + |
| part number | STP103OBGA-167 + |
| power dissipation (average) | 28 W (28,000 mW, 0.0375 hp, 0.028 kW) + |
| process | 500 nm (0.5 μm, 5.0e-4 mm) + |
| release price | $ 1,395.00 (€ 1,255.50, £ 1,129.95, ¥ 144,145.35) + |
| series | UltraSPARC-I + |
| technology | CMOS + |
| thread count | 1 + |
| transistor count | 5,200,000 + |
| word size | 64 bit (8 octets, 16 nibbles) + |