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Difference between revisions of "intel/microarchitectures/knights landing"
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|manufacturer=Intel
 
|manufacturer=Intel
 
|process=14 nm
 
|process=14 nm
 +
|cores=64
 +
|cores 2=68
 +
|cores 3=72
 
|type=Superscalar
 
|type=Superscalar
 
|oooe=Yes
 
|oooe=Yes
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|isa 2=x86-32
 
|isa 2=x86-32
 
|isa 3=x86-64
 
|isa 3=x86-64
−
 
+
|extension=AVX-512
−
| succession      = Yes
+
|l1i=32 kiB
−
| predecessor     = Knights Corner
+
|l1i per=core
−
| predecessor link = intel/microarchitectures/knights_corner
+
|l1d=32 kiB
−
| successor       = Knights Hill
+
|l1d per=core
−
| successor link   = intel/microarchitectures/knights_hill
+
|l1d desc=8-way associate
 +
|l2=1 MiB
 +
|l2 per=shared between cores within tile
 +
|core name=Silvermont
 +
|predecessor=Knights Corner
 +
|predecessor link=intel/microarchitectures/knights_corner
 +
|successor=Knights Hill
 +
|successor link=intel/microarchitectures/knights_hill
 +
|contemporary=Knights Mill
 +
|contemporary link=intel/microarchitectures/knights_mill
 +
|succession=Yes
 
}}
 
}}
−
'''Knights Landing''' ('''KNH''') is a [[many-core]] microarchitecture, produced by [[intel]] for high performance computing.
+
'''Knights Landing''' ('''KNL''') is the successor to {{\\|Knights Corner}}, a [[14 nm]] [[many-core]] microarchitecture designed by [[Intel]] for high performance computing.
  
 
== Process Technology ==
 
== Process Technology ==
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== Architecture ==
 
== Architecture ==
 +
=== Key changes from {{\\|Knights Corner}} ===
 
{{empty section}}
 
{{empty section}}
 +
==== New instructions ====
 +
Knights Landing introduced a number of {{x86|extensions|new instructions}}:
 +
 +
* {{x86|AVX-512|<code>AVX-512</code>}}, specifically:
 +
** {{x86|AVX512F|<code>AVX512F</code>}} - AVX-512 Foundation
 +
** {{x86|AVX512CD|<code>AVX512CD</code>}} - AVX-512 Conflict Detection
 +
** {{x86|AVX512BW|<code>AVX512PF</code>}} - Prefetch instructions for gather/scatter
 +
** {{x86|AVX512DQ|<code>AVX512ER</code>}} - Exponential and Reciprocal Instructions
  
 
== Die ==
 
== Die ==
−
Die shot of intel xeon phi, Knights Landing.
+
Die shot of Intel's Xeon Phi, Knights Landing.
  
 
* [[14 nm process]]
 
* [[14 nm process]]
 
* 682.6 mm² die size
 
* 682.6 mm² die size
−
* 72 CPU cores
+
* 76 CPU cores (sold with maximum 72 enabled cores)
 
* 7,100,000,000 transistors
 
* 7,100,000,000 transistors
  
 
[[File:intel xeon phi knightslanding die shot .jpeg|650px]]
 
[[File:intel xeon phi knightslanding die shot .jpeg|650px]]

Latest revision as of 12:25, 6 August 2018

Edit Values
Knights Landing µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
Process14 nm
Core Configs64, 68, 72
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Instructions
ISAx86-16, x86-32, x86-64
ExtensionsAVX-512
Cache
L1I Cache32 kiB/core
L1D Cache32 kiB/core
8-way associate
L2 Cache1 MiB/shared between cores within tile
Cores
Core NamesSilvermont
Succession
Contemporary
Knights Mill

Knights Landing (KNL) is the successor to Knights Corner, a 14 nm many-core microarchitecture designed by Intel for high performance computing.

Process Technology[edit]

See also: Broadwell § Process Technology and 14 nm lithography process

Knights Landing is fabricated on Intel's 14 nm process.

Architecture[edit]

Key changes from Knights Corner[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

New instructions[edit]

Knights Landing introduced a number of new instructions:

  • AVX-512, specifically:
    • AVX512F - AVX-512 Foundation
    • AVX512CD - AVX-512 Conflict Detection
    • AVX512PF - Prefetch instructions for gather/scatter
    • AVX512ER - Exponential and Reciprocal Instructions

Die[edit]

Die shot of Intel's Xeon Phi, Knights Landing.

  • 14 nm process
  • 682.6 mm² die size
  • 76 CPU cores (sold with maximum 72 enabled cores)
  • 7,100,000,000 transistors

intel xeon phi knightslanding die shot .jpeg

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/knights_landing&oldid=81154"
Facts about "Knights Landing - Microarchitectures - Intel"
RDF feed
codenameKnights Landing +
core count64 +, 68 + and 72 +
designerIntel +
full page nameintel/microarchitectures/knights landing +
instance ofmicroarchitecture +
instruction set architecturex86-16 +, x86-32 + and x86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameKnights Landing +
process14 nm (0.014 μm, 1.4e-5 mm) +