From WikiChip
Difference between revisions of "qualcomm/centriq/2452"
m (Bot: moving all {{mpu}} to {{chip}}) |
|||
(One intermediate revision by one other user not shown) | |||
Line 1: | Line 1: | ||
{{qualcomm title|Centriq 2452}} | {{qualcomm title|Centriq 2452}} | ||
− | {{ | + | {{chip |
|name=Centriq 2452 | |name=Centriq 2452 | ||
|image=falkor centriq 2400 (front).png | |image=falkor centriq 2400 (front).png | ||
Line 97: | Line 97: | ||
|vfpv5=No | |vfpv5=No | ||
|neon=Yes | |neon=Yes | ||
− | |trustzone= | + | |trustzone=Yes |
|jazelle=No | |jazelle=No | ||
|wmmx=No | |wmmx=No |
Latest revision as of 15:31, 13 December 2017
Edit Values | ||||||||||||
Centriq 2452 | ||||||||||||
General Info | ||||||||||||
Designer | Qualcomm | |||||||||||
Manufacturer | Samsung | |||||||||||
Model Number | 2452 | |||||||||||
Market | Server | |||||||||||
Introduction | November 8, 2017 (announced) November 8, 2017 (launched) | |||||||||||
Release Price | $1,383 | |||||||||||
General Specs | ||||||||||||
Family | Centriq | |||||||||||
Series | 2400 | |||||||||||
Frequency | 2,200 MHz | |||||||||||
Turbo Frequency | 2,600 MHz | |||||||||||
Microarchitecture | ||||||||||||
ISA | ARMv8 (ARM) | |||||||||||
Microarchitecture | Falkor | |||||||||||
Process | 10 nm | |||||||||||
Transistors | 18,000,000,000 | |||||||||||
Technology | CMOS | |||||||||||
Die | 398 mm² | |||||||||||
Word Size | 64 bit | |||||||||||
Cores | 46 | |||||||||||
Threads | 46 | |||||||||||
Max Memory | 768 GiB | |||||||||||
Multiprocessing | ||||||||||||
Max SMP | 1-Way (Uniprocessor) | |||||||||||
Electrical | ||||||||||||
Vcore | 1 V | |||||||||||
TDP | 120 W | |||||||||||
Packaging | ||||||||||||
|
Centriq 2452 is a 64-bit 46-core ARM high-performance server microprocessor designed by Qualcomm and introduced in late 2017. This processor, which is based on the Falkor microarchitecture, is fabricated on Samsung's 10LPE process. The 2452 has a base frequency of 2.2 GHz with a TDP of 120 W and a turbo frequency of 2.6 GHz. This chip supports up to 768 GiB of hexa-channel DDR4-2666 memory.
Contents
Cache[edit]
- Main article: Falkor § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
|||||||||||||||||||||||||||||||||||||
|
Memory controller[edit]
Integrated Memory Controller
|
||||||||||||||
|
Expansions[edit]
Expansion Options |
||||||||
|
Features[edit]
[Edit/Modify Supported Features]
Supported ARM Extensions & Processor Features
|
||||||||||||||
|
Facts about "Centriq 2452 - Qualcomm"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Centriq 2452 - Qualcomm#pcie + |
has ecc memory support | true + |
l1$ size | 4,416 KiB (4,521,984 B, 4.313 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 1,472 KiB (1,507,328 B, 1.438 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 2,944 KiB (3,014,656 B, 2.875 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 11.5 MiB (11,776 KiB, 12,058,624 B, 0.0112 GiB) + |
l3$ description | 20-way set associative + |
l3$ size | 57.5 MiB (58,880 KiB, 60,293,120 B, 0.0562 GiB) + |
max memory bandwidth | 119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) + |
max memory channels | 6 + |
max sata ports | 8 + |
supported memory type | DDR4-2666 + |