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Difference between revisions of "qualcomm/centriq/2452"
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{{qualcomm title|Centriq 2452}}
 
{{qualcomm title|Centriq 2452}}
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{{mpu
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{{chip
 
|name=Centriq 2452
 
|name=Centriq 2452
 
|image=falkor centriq 2400 (front).png
 
|image=falkor centriq 2400 (front).png
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|v core=1 V
 
|v core=1 V
 
|tdp=120 W
 
|tdp=120 W
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|package module 1={{packages/qualcomm/fcbga-2808}}
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|package module 1={{packages/qualcomm/fclga-2808}}
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}}
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'''Centriq 2452''' is a {{arch|64}} [[46-core]] [[ARM]] high-performance server microprocessor designed by [[Qualcomm]] and introduced in late 2017. This processor, which is based on the {{qualcomm|Falkor|l=arch}} microarchitecture, is fabricated on [[Samsung]]'s [[10 nm process|10LPE process]]. The 2452 has a base frequency of 2.2 GHz with a TDP of 120 W and a turbo frequency of 2.6 GHz. This chip supports up to 768 GiB of hexa-channel DDR4-2666 memory.
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 +
== Cache ==
 +
{{main|qualcomm/microarchitectures/falkor#Memory_Hierarchy|l1=Falkor § Cache}}
 +
{{cache size
 +
|l1 cache=4.3125 MiB
 +
|l1i cache=2.875 MiB
 +
|l1i break=46x64 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=1.4375 MiB
 +
|l1d break=46x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=write-through
 +
|l2 cache=11.5 MiB
 +
|l2 break=20x512 KiB
 +
|l2 desc=8-way set associative
 +
|l3 cache=57.5 MiB
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|l3 break=11.5x5 MiB
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|l3 desc=20-way set associative
 +
}}
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== Memory controller ==
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{{memory controller
 +
|type=DDR4-2666
 +
|ecc=Yes
 +
|max mem=768 GiB
 +
|controllers=6
 +
|channels=6
 +
|max bandwidth=119.21 GiB/s
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|bandwidth schan=19.87 GiB/s
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|bandwidth dchan=39.74 GiB/s
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|bandwidth qchan=79.47 GiB/s
 +
|bandwidth hchan=119.21 GiB/s
 +
}}
 +
 
 +
== Expansions ==
 +
{{expansions main
 +
|
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{{expansions entry
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|type=PCIe
 +
|pcie revision=3.0
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|pcie lanes=32
 +
|pcie config=x16
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|pcie config 2=x8
 +
|pcie config 3=x4
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}}
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{{expansions entry
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|type=SATA
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|sata revision=3.0
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|sata ports=8
 +
}}
 +
}}
 +
 
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== Features ==
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{{arm features
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|thumb=No
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|thumb2=No
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|thumbee=No
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|vfpv1=No
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|vfpv2=No
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|vfpv3=No
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|vfpv3-d16=No
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|vfpv3-f16=No
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|vfpv4=No
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|vfpv4-d16=No
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|vfpv5=No
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|neon=Yes
 +
|trustzone=Yes
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|jazelle=No
 +
|wmmx=No
 +
|wmmx2=No
 +
|pmuv3=Yes
 +
|crc32=Yes
 +
|crypto=Yes
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|fp=Yes
 +
|fp16=No
 +
|profile=No
 +
|ras=No
 +
|simd=No
 +
|rdm=Yes
 
}}
 
}}
−
'''Centriq 2452''' is a {{arch|64}} [[46-core]] [[ARM]] high-performance server microprocessor designed by [[Qualcomm]] and introduced in late 2017.
 

Latest revision as of 15:31, 13 December 2017

Edit Values
Centriq 2452
falkor centriq 2400 (front).png
General Info
DesignerQualcomm
ManufacturerSamsung
Model Number2452
MarketServer
IntroductionNovember 8, 2017 (announced)
November 8, 2017 (launched)
Release Price$1,383
General Specs
FamilyCentriq
Series2400
Frequency2,200 MHz
Turbo Frequency2,600 MHz
Microarchitecture
ISAARMv8 (ARM)
MicroarchitectureFalkor
Process10 nm
Transistors18,000,000,000
TechnologyCMOS
Die398 mm²
Word Size64 bit
Cores46
Threads46
Max Memory768 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Vcore1 V
TDP120 W
Packaging
PackageFCLGA-2808 (LGA)falkor centriq 2400 (back).png
Dimension55 mm x 55 mm
Pitch1 mm
Contacts2808
SocketLGA-2808

Centriq 2452 is a 64-bit 46-core ARM high-performance server microprocessor designed by Qualcomm and introduced in late 2017. This processor, which is based on the Falkor microarchitecture, is fabricated on Samsung's 10LPE process. The 2452 has a base frequency of 2.2 GHz with a TDP of 120 W and a turbo frequency of 2.6 GHz. This chip supports up to 768 GiB of hexa-channel DDR4-2666 memory.

Cache[edit]

Main article: Falkor § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$4.3125 MiB
4,416 KiB
4,521,984 B
L1I$2.875 MiB
2,944 KiB
3,014,656 B
46x64 KiB8-way set associative 
L1D$1.4375 MiB
1,472 KiB
1,507,328 B
46x32 KiB8-way set associativewrite-through
L2$11.5 MiB
11,776 KiB
12,058,624 B
0.0112 GiB
  20x512 KiB8-way set associative 
L3$57.5 MiB
58,880 KiB
60,293,120 B
0.0562 GiB
  11.5x5 MiB20-way set associative 

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666
Supports ECCYes
Max Mem768 GiB
Controllers6
Channels6
Max Bandwidth119.21 GiB/s
122,071.04 MiB/s
128.001 GB/s
128,000.763 MB/s
0.116 TiB/s
0.128 TB/s
Bandwidth
Single 19.87 GiB/s
Double 39.74 GiB/s
Quad 79.47 GiB/s
Hexa 119.21 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 32
Configuration: x16, x8, x4
SATARevision: 3.0
Max Ports: 8


Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
NEONAdvanced SIMD extension
TrustZoneTrustZone Security Extensions
PMUv3ARMv8 PMUv3 Performance Monitors Extension
CRC32CRC-32 checksum Extension
CryptoCryptographic Extension
FPFloating-point Extension
RDMARMv8.1 Rounding Double Multiply Add/Subtract
Retrieved from "https://en.wikichip.org/w/index.php?title=qualcomm/centriq/2452&oldid=71165"
Facts about "Centriq 2452 - Qualcomm"
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Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Centriq 2452 - Qualcomm#package + and Centriq 2452 - Qualcomm#pcie +
base frequency2,200 MHz (2.2 GHz, 2,200,000 kHz) +
core count46 +
core voltage1 V (10 dV, 100 cV, 1,000 mV) +
designerQualcomm +
die area398 mm² (0.617 in², 3.98 cm², 398,000,000 µm²) +
familyCentriq +
first announcedNovember 8, 2017 +
first launchedNovember 8, 2017 +
full page namequalcomm/centriq/2452 +
has ecc memory supporttrue +
instance ofmicroprocessor +
isaARMv8 +
isa familyARM +
l1$ size4,416 KiB (4,521,984 B, 4.313 MiB) +
l1d$ description8-way set associative +
l1d$ size1,472 KiB (1,507,328 B, 1.438 MiB) +
l1i$ description8-way set associative +
l1i$ size2,944 KiB (3,014,656 B, 2.875 MiB) +
l2$ description8-way set associative +
l2$ size11.5 MiB (11,776 KiB, 12,058,624 B, 0.0112 GiB) +
l3$ description20-way set associative +
l3$ size57.5 MiB (58,880 KiB, 60,293,120 B, 0.0562 GiB) +
ldateNovember 8, 2017 +
main imageFile:falkor centriq 2400 (front).png +
manufacturerSamsung +
market segmentServer +
max cpu count1 +
max memory786,432 MiB (805,306,368 KiB, 824,633,720,832 B, 768 GiB, 0.75 TiB) +
max memory bandwidth119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels6 +
max sata ports8 +
microarchitectureFalkor +
model number2452 +
nameCentriq 2452 +
packageFCLGA-2808 +
process10 nm (0.01 μm, 1.0e-5 mm) +
release price$ 1,383.00 (€ 1,244.70, £ 1,120.23, ¥ 142,905.39) +
series2400 +
smp max ways1 +
socketLGA-2808 +
supported memory typeDDR4-2666 +
tdp120 W (120,000 mW, 0.161 hp, 0.12 kW) +
technologyCMOS +
thread count46 +
transistor count18,000,000,000 +
turbo frequency2,600 MHz (2.6 GHz, 2,600,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +