Semiconductor & Computer Engineering
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{{intel title|Turbo Boost Technology (TBT)}} | {{intel title|Turbo Boost Technology (TBT)}} | ||
| − | '''[[name::Turbo Boost Technology]]''' ('''TBT''') is a [[microprocessor]] [[instance of::technology]] developed by [[designer::Intel]] that attempts to enable temporary higher performance by opportunistically and automatically increasing the processor's [[clock generator|clock]] frequency. This feature automatically kicks in on TBT-enabled processors | + | '''[[name::Turbo Boost Technology]]''' ('''TBT''') is a [[microprocessor]] [[instance of::technology]] developed by [[designer::Intel]] that attempts to enable temporary higher performance by opportunistically and automatically increasing the processor's [[clock generator|clock]] frequency. This feature automatically kicks in on TBT-enabled processors when there is sufficient headroom - subject to power rating, temperature rating, and current limits. |
== History == | == History == | ||
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== Mechanism == | == Mechanism == | ||
| − | This feature is only available on [[Intel]] microprocessors that support Turbo Boost and have the feature enabled and supported (e.g. most [[operating system|OSs]]). Under various workloads, especially | + | This feature is only available on [[Intel]] microprocessors that support Turbo Boost and have the feature enabled and supported (e.g. most [[operating system|OSs]]). Under various workloads, especially ones that are relatively low in power demands and are lightly threaded or not threaded at all, the processor can take advantage of the headroom by increasing the [[clock generator|clock]] frequency - while staying within thermal and electrical limits. The decision to kick into turbo boost is automatic and algorithmic in nature based on a number of factors such as: estimated current consumption, estimated power consumption, core temperature, and the number of active cores. |
The number of '''active cores''', which Intel defines as cores in "C0" or "C1" states ("C3" and "C6" states are 'inactive'), dictates the upper limit. Generally, the more active cores, the lower the highest clock frequency Turbo Boost can allow as it's easier to exceed various electrical limits. For example, a [[dual-core]] 2 GHz MPU may allow a boost of 266.66 MHz (to 2266.66 MHz) when a single core is active but only 133.33 MHz (to 2133.33 MHz) when two cores are active. (Note that if the thermal and electrical limits have been exceeded, Turbo Boost will be limited even further). The notion of active cores is important because disabling [[advanced configuration and power interface|ACPI]] (e.g. C3) in an attempt to beef up performance also has the counter-consequence of potentially reducing single-core performance (as that prevents Turbo Boost from reaching maximum allowable frequency). | The number of '''active cores''', which Intel defines as cores in "C0" or "C1" states ("C3" and "C6" states are 'inactive'), dictates the upper limit. Generally, the more active cores, the lower the highest clock frequency Turbo Boost can allow as it's easier to exceed various electrical limits. For example, a [[dual-core]] 2 GHz MPU may allow a boost of 266.66 MHz (to 2266.66 MHz) when a single core is active but only 133.33 MHz (to 2133.33 MHz) when two cores are active. (Note that if the thermal and electrical limits have been exceeded, Turbo Boost will be limited even further). The notion of active cores is important because disabling [[advanced configuration and power interface|ACPI]] (e.g. C3) in an attempt to beef up performance also has the counter-consequence of potentially reducing single-core performance (as that prevents Turbo Boost from reaching maximum allowable frequency). | ||
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{| class="wikitable" | {| class="wikitable" | ||
|- | |- | ||
| − | ! µarch !! {{x86|BCLK}} | + | ! µarch !! {{x86|BCLK}} || || µarch !! {{x86|BCLK}} |
|- | |- | ||
| − | | {{intel|Nehalem|l=arch}} || 133.<span style="text-decoration:overline">33</span> MHz | + | | {{intel|Nehalem|l=arch}} || 133.<span style="text-decoration:overline">33</span> MHz || || {{intel|Cascade Lake|l=arch}} || 100.00 MHz |
|- | |- | ||
| − | | {{intel|Westmere|l=arch}} || 133.<span style="text-decoration:overline">33</span> MHz | + | | {{intel|Westmere|l=arch}} || 133.<span style="text-decoration:overline">33</span> MHz || || {{intel|Cannon Lake|l=arch}} || 100.00 MHz |
|- | |- | ||
| − | | {{intel|Sandy Bridge|l=arch}} || 100.00 MHz | + | | {{intel|Sandy Bridge|l=arch}} || 100.00 MHz || || {{intel|Ice Lake|l=arch}} || 100.00 MHz |
|- | |- | ||
| {{intel|Ivy Bridge|l=arch}} || 100.00 MHz | | {{intel|Ivy Bridge|l=arch}} || 100.00 MHz | ||
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== See also== | == See also== | ||
* {{intel|Dynamic Acceleration|Intel Dynamic Acceleration}} (IDA) | * {{intel|Dynamic Acceleration|Intel Dynamic Acceleration}} (IDA) | ||
| + | * {{intel|Turbo Boost Max Technology|Turbo Boost Max Technology}} (TBMT) | ||
| − | + | [[Category:power management mechanisms by intel]] | |
| − | [[Category:power management | ||
Latest revision as of 13:39, 23 July 2022
Turbo Boost Technology (TBT) is a microprocessor technology developed by Intel that attempts to enable temporary higher performance by opportunistically and automatically increasing the processor's clock frequency. This feature automatically kicks in on TBT-enabled processors when there is sufficient headroom - subject to power rating, temperature rating, and current limits.
Contents
History[edit]
Turbo Boost Technology 1.0 was first introduced announced in a white paper Intel published in November 2008. It was consequently introduced in the Nehalem microarchitecture. Turbo Boost 2.0 was introduced later in 2011 in the Sandy Bridge microarchitecture.
Mechanism[edit]
This feature is only available on Intel microprocessors that support Turbo Boost and have the feature enabled and supported (e.g. most OSs). Under various workloads, especially ones that are relatively low in power demands and are lightly threaded or not threaded at all, the processor can take advantage of the headroom by increasing the clock frequency - while staying within thermal and electrical limits. The decision to kick into turbo boost is automatic and algorithmic in nature based on a number of factors such as: estimated current consumption, estimated power consumption, core temperature, and the number of active cores.
The number of active cores, which Intel defines as cores in "C0" or "C1" states ("C3" and "C6" states are 'inactive'), dictates the upper limit. Generally, the more active cores, the lower the highest clock frequency Turbo Boost can allow as it's easier to exceed various electrical limits. For example, a dual-core 2 GHz MPU may allow a boost of 266.66 MHz (to 2266.66 MHz) when a single core is active but only 133.33 MHz (to 2133.33 MHz) when two cores are active. (Note that if the thermal and electrical limits have been exceeded, Turbo Boost will be limited even further). The notion of active cores is important because disabling ACPI (e.g. C3) in an attempt to beef up performance also has the counter-consequence of potentially reducing single-core performance (as that prevents Turbo Boost from reaching maximum allowable frequency).
Some BIOS may allow for Turbo Boost to be disabled or enabled. Additionally, Turbo Boosts operates under the operating system's control and is engaged automatically when the OS requests the highest performance state ("P0"). The amount of time the processors remains in Turbo Boosts depends on the workload and OS requests. When Turbo Boost is active on a single core, it's active on all cores.
Upper limit based on active core count[edit]
The upper frequency limit depends on the active core count and the microarchitecture's BCLK. The turbo frequency per each number of active cores is some multiple (called a bin upside) of the base clock, which is listed below. The exact multiplier is model-dependent.
| µarch | BCLK | µarch | BCLK | |
|---|---|---|---|---|
| Nehalem | 133.33 MHz | Cascade Lake | 100.00 MHz | |
| Westmere | 133.33 MHz | Cannon Lake | 100.00 MHz | |
| Sandy Bridge | 100.00 MHz | Ice Lake | 100.00 MHz | |
| Ivy Bridge | 100.00 MHz | |||
| Haswell | 100.00 MHz | |||
| Broadwell | 100.00 MHz | |||
| Skylake | 100.00 MHz | |||
| Kaby Lake | 100.00 MHz | |||
| Coffee Lake | 100.00 MHz |
Programmatically[edit]
The information about the upper limit of Turbo Boost for a specific processor can be obtained programmatically through the use of the Model-specific register. The value is the ratio (or multiplier) of BCLK.
For examples as to how it's done, see dump_nhm_turbo_ratio_limits(), dump_ivt_turbo_ratio_limits(), and dump_hsw_turbo_ratio_limits().
Example[edit]
The Sandy Bridge-based dual-core i7-2677M has a base frequency of 1.8 GHz. It also has a Turbo Boost Bin Upside of 11 and 8. Therefore it has a Turbo Boost max frequency of 2.9 GHz for 1 core
- 1,800 MHz + 11x100 MHz = 2,900 MHz,
and 2.6 GHz for 2 cores
- 1,800 MHz + 8x100 MHz = 2,600 MHz.
Similarly, the Sandy Bridge-based quad-core i7-2960XM has a base frequency of 2.7 GHz and Turbo Boost Bin Upside of 10, 9, 8, and 8. Therefore it has a Turbo Boost max frequency of 3.7 GHz for 1 core
- 2,700 MHz + 10x100 MHz = 3,700 MHz,
3.6 GHz for 2 cores
- 2,700 MHz + 9x100 MHz = 3,600 MHz,
and 3.5 GHz fore when both 3 and 4 cores are active.
- 2,700 MHz + 8x100 MHz = 3,500 MHz
| Turbo Boost Example | ||||||
|---|---|---|---|---|---|---|
| Processor | i7-2677M | i7-2960XM | ||||
| Bin | 100 MHz | 100 MHz | ||||
| Core Setup | Dual-core | Quad-core | ||||
| Active Cores | 1C | 2C | 1C | 2C | 3C | 4C |
| Turbo Boost Bin Upside | 11 | 8 | 10 | 9 | 8 | 8 |
| Turbo Boost Frequency | 2.9 GHz | 2.6 GHz | 3.7 GHz | 3.6 GHz | 3.5 GHZ | 3.5 GHz |
Supported Processors[edit]
See also[edit]
- Intel Dynamic Acceleration (IDA)
- Turbo Boost Max Technology (TBMT)
| designer | Intel + |
| first launched | November 2008 + |
| instance of | technology + |
| name | Turbo Boost Technology + |