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Difference between revisions of "freescale/qoriq/p2010"
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{{freescale title|QorIQ P2010}} | {{freescale title|QorIQ P2010}} | ||
− | {{ | + | {{chip |
|name=P2010 | |name=P2010 | ||
− | | | + | |image=qoriq p2020.png |
|designer=Freescale | |designer=Freescale | ||
|manufacturer=IBM | |manufacturer=IBM | ||
Line 10: | Line 10: | ||
|first announced=June 16, 2008 | |first announced=June 16, 2008 | ||
|first launched=2009 | |first launched=2009 | ||
+ | |last order=2023 | ||
|family=QorIQ | |family=QorIQ | ||
|series=P2 | |series=P2 | ||
− | |frequency=1,200 MHz | + | |frequency=800 MHz |
+ | |frequency 2=1,000 MHz | ||
+ | |frequency 3=1,200 MHz | ||
+ | |frequency 4=1,333 MHz | ||
|isa=Power ISA v2.03 | |isa=Power ISA v2.03 | ||
|isa family=Power | |isa family=Power | ||
|microarch=e500 | |microarch=e500 | ||
− | |core name=e500 | + | |core name=e500 v2 |
|process=45 nm | |process=45 nm | ||
|technology=CMOS | |technology=CMOS | ||
Line 22: | Line 26: | ||
|core count=1 | |core count=1 | ||
|thread count=1 | |thread count=1 | ||
+ | |power=6.7 W | ||
|tjunc min=0 °C | |tjunc min=0 °C | ||
|tjunc max=125 °C | |tjunc max=125 °C | ||
|package module 1={{packages/freescale/te-pbga-ii-689}} | |package module 1={{packages/freescale/te-pbga-ii-689}} | ||
}} | }} | ||
+ | '''QorIQ P2010''' is a {{arch|32}} embedded [[POWER]] microprocessor introduced by [[Freescale]] in [[2008]]. This networking/embedded processor, which is based on the {{freescale|e500|l=arch}} microarchitecture and is fabricated on a [[45 nm SOI process]], operates at 1.2 GHz and supports 64-bit DDR3-800 memory. | ||
+ | |||
+ | == Cache == | ||
+ | {{main|freescale/microarchitectures/e500#Memory_Hierarchy|l1=e500 § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=64 KiB | ||
+ | |l1i cache=32 KiB | ||
+ | |l1i break=1x32 KiB | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d cache=32 KiB | ||
+ | |l1d break=1x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d policy= | ||
+ | |l2 cache=512 KiB | ||
+ | |l2 break=1x512 KiB | ||
+ | |l2 desc=8-way set associative | ||
+ | |l2 policy=Write-through | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR3-800 | ||
+ | |ecc=Yes | ||
+ | |controllers=1 | ||
+ | |channels=1 | ||
+ | |width=64 bit | ||
+ | |max bandwidth=5.96 GiB/s | ||
+ | |bandwidth schan=5.96 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | * 3x 10/100/1000 Eithernet with SGMII | ||
+ | * 3x PCIe 1.0a controllers with 2 SerDes | ||
+ | * 1x USB 2.0 | ||
+ | * SD/MMC | ||
+ | * SPI | ||
+ | * 2x I2C | ||
+ | * UART | ||
+ | * SEC 3.1 Security Acceleration | ||
+ | |||
+ | == Block Diagram == | ||
+ | : [[File:qoriq p2010 block diagram.png|800px]] | ||
+ | |||
+ | == Documents == | ||
+ | * [[:File:QorIQ P2.pdf|QorIQ P2 Series Product Brief]] | ||
+ | * [[:File:P2 Family App Bro.pdf|P2 Platform Series]] |
Latest revision as of 12:32, 5 April 2020
Edit Values | |||||||
P2010 | |||||||
General Info | |||||||
Designer | Freescale | ||||||
Manufacturer | IBM | ||||||
Model Number | P2010 | ||||||
Market | Networking, Embedded | ||||||
Introduction | June 16, 2008 (announced) 2009 (launched) | ||||||
End-of-life | 2023 (last order) | ||||||
General Specs | |||||||
Family | QorIQ | ||||||
Series | P2 | ||||||
Frequency | 800 MHz, 1,000 MHz, 1,200 MHz, 1,333 MHz | ||||||
Microarchitecture | |||||||
ISA | Power ISA v2.03 (Power) | ||||||
Microarchitecture | e500 | ||||||
Core Name | e500 v2 | ||||||
Process | 45 nm | ||||||
Technology | CMOS | ||||||
Word Size | 32 bit | ||||||
Cores | 1 | ||||||
Threads | 1 | ||||||
Electrical | |||||||
Power dissipation | 6.7 W | ||||||
Tjunction | 0 °C – 125 °C | ||||||
Packaging | |||||||
|
QorIQ P2010 is a 32-bit embedded POWER microprocessor introduced by Freescale in 2008. This networking/embedded processor, which is based on the e500 microarchitecture and is fabricated on a 45 nm SOI process, operates at 1.2 GHz and supports 64-bit DDR3-800 memory.
Cache[edit]
- Main article: e500 § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Expansions[edit]
- 3x 10/100/1000 Eithernet with SGMII
- 3x PCIe 1.0a controllers with 2 SerDes
- 1x USB 2.0
- SD/MMC
- SPI
- 2x I2C
- UART
- SEC 3.1 Security Acceleration
Block Diagram[edit]
Documents[edit]
Facts about "QorIQ P2010 - Freescale"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | QorIQ P2010 - Freescale#package + |
base frequency | 800 MHz (0.8 GHz, 800,000 kHz) +, 1,000 MHz (1 GHz, 1,000,000 kHz) +, 1,200 MHz (1.2 GHz, 1,200,000 kHz) + and 1,333 MHz (1.333 GHz, 1,333,000 kHz) + |
core count | 1 + |
core name | e500 v2 + |
designer | Freescale + |
family | QorIQ + |
first announced | June 16, 2008 + |
first launched | 2009 + |
full page name | freescale/qoriq/p2010 + |
has ecc memory support | true + |
instance of | microprocessor + |
isa | Power ISA v2.03 + |
isa family | Power + |
l1$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
last order | 2023 + |
ldate | 2009 + |
main image | + |
manufacturer | IBM + |
market segment | Networking + and Embedded + |
max junction temperature | 398.15 K (125 °C, 257 °F, 716.67 °R) + |
max memory bandwidth | 5.96 GiB/s (6,103.04 MiB/s, 6.4 GB/s, 6,399.501 MB/s, 0.00582 TiB/s, 0.0064 TB/s) + |
max memory channels | 1 + |
microarchitecture | e500 + |
min junction temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
model number | P2010 + |
name | P2010 + |
package | TE-PBGA-II-689 + |
power dissipation | 6.7 W (6,700 mW, 0.00898 hp, 0.0067 kW) + |
process | 45 nm (0.045 μm, 4.5e-5 mm) + |
series | P2 + |
supported memory type | DDR3-800 + |
technology | CMOS + |
thread count | 1 + |
word size | 32 bit (4 octets, 8 nibbles) + |