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Difference between revisions of "freescale/qoriq/p1020"
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{{freescale title|QorIQ P1020}} | {{freescale title|QorIQ P1020}} | ||
− | {{ | + | {{chip |
− | |name=P1020 | + | |name=QorIQ P1020 |
|no image=Yes | |no image=Yes | ||
+ | |image=qoriq freescale pbgaii.png | ||
|designer=Freescale | |designer=Freescale | ||
|manufacturer=IBM | |manufacturer=IBM | ||
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|isa family=Power | |isa family=Power | ||
|microarch=e500 | |microarch=e500 | ||
− | |core name=e500 | + | |core name=e500 v2 |
|process=45 nm | |process=45 nm | ||
|technology=CMOS | |technology=CMOS | ||
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|core count=2 | |core count=2 | ||
|thread count=2 | |thread count=2 | ||
+ | |power=1.89 W | ||
|tjunc min=0 °C | |tjunc min=0 °C | ||
|tjunc max=125 °C | |tjunc max=125 °C | ||
|package module 1={{packages/freescale/te-pbga-ii-689}} | |package module 1={{packages/freescale/te-pbga-ii-689}} | ||
}} | }} | ||
− | '''QorIQ P1020''' is a {{arch|32}} embedded [[dual-core]] [[POWER]] microprocessor introduced by [[Freescale]] in [[2008]]. This networking/embedded processor, which is based on the {{freescale|e500|l=arch}} microarchitecture and is fabricated on a [[45 nm SOI process]], operates at 1.2 GHz and supports 32-bit | + | '''QorIQ P1020''' is a {{arch|32}} embedded [[dual-core]] [[POWER]] microprocessor introduced by [[Freescale]] in [[2008]]. This networking/embedded processor, which is based on the {{freescale|e500|l=arch}} microarchitecture and is fabricated on a [[45 nm SOI process]], operates at 1.2 GHz and supports 32-bit DDR3-800 memory. |
+ | |||
+ | == Cache == | ||
+ | {{main|freescale/microarchitectures/e500#Memory_Hierarchy|l1=e500 § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=128 KiB | ||
+ | |l1i cache=64 KiB | ||
+ | |l1i break=2x32 KiB | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d cache=64 KiB | ||
+ | |l1d break=2x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d policy= | ||
+ | |l2 cache=256 KiB | ||
+ | |l2 break=1x256 KiB | ||
+ | |l2 desc=8-way set associative | ||
+ | |l2 policy=Write-through | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR3-800 | ||
+ | |ecc=Yes | ||
+ | |controllers=1 | ||
+ | |channels=1 | ||
+ | |width=32 bit | ||
+ | |max bandwidth=2.98 GiB/s | ||
+ | |bandwidth schan=2.98 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | * 2x 10/100/1000 Eithernet with 2x SGMII | ||
+ | * 2x PCIe 1.0a controllers with 2 SerDes | ||
+ | * 2x USB 2.0 | ||
+ | * SD/MMC | ||
+ | * SPI | ||
+ | * 2x I2C | ||
+ | * UART | ||
+ | * SEC 3.1 Security Acceleration | ||
+ | |||
+ | == Block Diagram == | ||
+ | : [[File:qoriq p1020 block diagram.png|800px]] | ||
+ | |||
+ | == Documents == | ||
+ | * [[:File:QorIQ P1.pdf|QorIQ P1 Series Product Brief]] |
Latest revision as of 15:13, 13 December 2017
Edit Values | |||||||
QorIQ P1020 | |||||||
General Info | |||||||
Designer | Freescale | ||||||
Manufacturer | IBM | ||||||
Model Number | P1020 | ||||||
Market | Networking, Embedded | ||||||
Introduction | June 16, 2008 (announced) 2009 (launched) | ||||||
General Specs | |||||||
Family | QorIQ | ||||||
Series | P1 | ||||||
Frequency | 800 MHz | ||||||
Microarchitecture | |||||||
ISA | Power ISA v2.03 (Power) | ||||||
Microarchitecture | e500 | ||||||
Core Name | e500 v2 | ||||||
Process | 45 nm | ||||||
Technology | CMOS | ||||||
Word Size | 32 bit | ||||||
Cores | 2 | ||||||
Threads | 2 | ||||||
Electrical | |||||||
Power dissipation | 1.89 W | ||||||
Tjunction | 0 °C – 125 °C | ||||||
Packaging | |||||||
|
QorIQ P1020 is a 32-bit embedded dual-core POWER microprocessor introduced by Freescale in 2008. This networking/embedded processor, which is based on the e500 microarchitecture and is fabricated on a 45 nm SOI process, operates at 1.2 GHz and supports 32-bit DDR3-800 memory.
Cache[edit]
- Main article: e500 § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Expansions[edit]
- 2x 10/100/1000 Eithernet with 2x SGMII
- 2x PCIe 1.0a controllers with 2 SerDes
- 2x USB 2.0
- SD/MMC
- SPI
- 2x I2C
- UART
- SEC 3.1 Security Acceleration
Block Diagram[edit]
Documents[edit]
Facts about "QorIQ P1020 - Freescale"
has ecc memory support | true + |
l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) + |
max memory bandwidth | 2.98 GiB/s (3,051.52 MiB/s, 3.2 GB/s, 3,199.751 MB/s, 0.00291 TiB/s, 0.0032 TB/s) + |
max memory channels | 1 + |
supported memory type | DDR3-800 + |