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Difference between revisions of "intel/core i5/i5-2475m"
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Latest revision as of 16:19, 13 December 2017
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Core i5-2475M | |||||||||
General Info | |||||||||
Designer | Intel | ||||||||
Manufacturer | Intel | ||||||||
Model Number | i5-2475M | ||||||||
Part Number | AV8062700845507 | ||||||||
S-Spec | SR06X | ||||||||
Market | Mobile | ||||||||
Introduction | 2012 (announced) 2012 (launched) | ||||||||
Shop | Amazon | ||||||||
General Specs | |||||||||
Family | Core i5 | ||||||||
Series | i5-2000 | ||||||||
Locked | Yes | ||||||||
Frequency | 2,600 MHz | ||||||||
Bus type | DMI 2.0 | ||||||||
Bus rate | 4 × 5 GT/s | ||||||||
Clock multiplier | 26 | ||||||||
CPUID | 0x206A7 | ||||||||
Microarchitecture | |||||||||
ISA | x86-64 (x86) | ||||||||
Microarchitecture | Sandy Bridge | ||||||||
Platform | Sandy Bridge M | ||||||||
Chipset | Cougar Point | ||||||||
Core Name | Sandy Bridge M | ||||||||
Core Family | 6 | ||||||||
Core Model | 42 | ||||||||
Core Stepping | J1 | ||||||||
Process | 32 nm | ||||||||
Transistors | 624,000,000 | ||||||||
Technology | CMOS | ||||||||
Die | 149 mm² | ||||||||
Word Size | 64 bit | ||||||||
Cores | 2 | ||||||||
Threads | 4 | ||||||||
Max Memory | 16 GiB | ||||||||
Multiprocessing | |||||||||
Max SMP | 1-Way (Uniprocessor) | ||||||||
Electrical | |||||||||
Power (idle) | 3.1 W | ||||||||
Vcore | 0.3 V-1.52 V | ||||||||
TDP | 35 W | ||||||||
Tjunction | 0 °C – 100 °C | ||||||||
Tstorage | -25 °C – 125 °C | ||||||||
Packaging | |||||||||
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Core i5-2475M is a dual-core mid-range performance mobile x86 microprocessor introduced by Intel in 2012. This chip, which is fabricated on a 32 nm process based on the Sandy Bridge microarchitecture, operates at 2.6 GHz with a TDP of 35 Watts and a Turbo Boost frequency of up to ? GHz. The i5-2475M incorporates HD Graphics 3000 integrated graphics operating at 650 MHz with a burst frequency of 1.3 GHz and supports up to 16 GiB of dual-channel DDR3-1333 memory.
Cache[edit]
- Main article: Sandy Bridge § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options |
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Wireless[edit]
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Cellular | ||||
4G |
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Graphics[edit]
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Integrated Graphics Information
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[Edit] Sandy Bridge (Gen6) Hardware Accelerated Video Capabilities | |||||||
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Codec | Encode | Decode | |||||
Profiles | Levels | Max Resolution | Profiles | Levels | Max Resolution | ||
MPEG-2 (H.262) | ✘ | Main | Main, High | Up to 80 Mbps | |||
MPEG-4 AVC (H.264) | Main | 4.1 | Up to 40 Mbps | Main, High | 4.1 | Up to 40 Mbps | |
VC-1 | ✘ | Advanced, Main, Simple | 3, High, Simple | Up to 40 Mbps |
Features[edit]
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Facts about "Core i5-2475M - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Core i5-2475M - Intel#pcie + |
device id | 0x116 + |
has 4g support | true + |
has ecc memory support | false + |
has wimax support | true + |
integrated gpu | HD Graphics 3000 + |
integrated gpu base frequency | 650 MHz (0.65 GHz, 650,000 KHz) + |
integrated gpu designer | Intel + |
integrated gpu execution units | 12 + |
integrated gpu max frequency | 1,300 MHz (1.3 GHz, 1,300,000 KHz) + |
l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
l3$ description | 12-way set associative + |
l3$ size | 3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) + |
max memory bandwidth | 19.87 GiB/s (20,346.88 MiB/s, 21.335 GB/s, 21,335.25 MB/s, 0.0194 TiB/s, 0.0213 TB/s) + |
max memory channels | 2 + |
supported memory type | DDR3-1333 + and DDR3-1066 + |