From WikiChip
Difference between revisions of "intel/core i5/i5-2410m"
m (Bot: moving all {{mpu}} to {{chip}}) |
|||
Line 1: | Line 1: | ||
{{intel title|Core i5-2410M}} | {{intel title|Core i5-2410M}} | ||
− | {{ | + | {{chip |
|name=Core i5-2410M | |name=Core i5-2410M | ||
|no image=Yes | |no image=Yes |
Latest revision as of 16:19, 13 December 2017
Edit Values | |||||||||||
Core i5-2410M | |||||||||||
General Info | |||||||||||
Designer | Intel | ||||||||||
Manufacturer | Intel | ||||||||||
Model Number | i5-2410M | ||||||||||
Part Number | FF8062700845205, AV8062700845406 | ||||||||||
S-Spec | SR04B, SR04G | ||||||||||
Market | Mobile | ||||||||||
Introduction | February, 2011 (announced) February, 2011 (launched) | ||||||||||
Release Price | $225 | ||||||||||
Shop | Amazon | ||||||||||
General Specs | |||||||||||
Family | Core i5 | ||||||||||
Series | i5-2000 | ||||||||||
Locked | Yes | ||||||||||
Frequency | 2,300 MHz | ||||||||||
Turbo Frequency | 2,900 MHz (1 core), 2,700 MHz (2 cores) | ||||||||||
Bus type | DMI 2.0 | ||||||||||
Bus rate | 4 × 5 GT/s | ||||||||||
Clock multiplier | 23 | ||||||||||
CPUID | 0x206A7 | ||||||||||
Microarchitecture | |||||||||||
ISA | x86-64 (x86) | ||||||||||
Microarchitecture | Sandy Bridge | ||||||||||
Platform | Sandy Bridge M | ||||||||||
Chipset | Cougar Point | ||||||||||
Core Name | Sandy Bridge M | ||||||||||
Core Family | 6 | ||||||||||
Core Model | 42 | ||||||||||
Core Stepping | J1 | ||||||||||
Process | 32 nm | ||||||||||
Transistors | 624,000,000 | ||||||||||
Technology | CMOS | ||||||||||
Die | 149 mm² | ||||||||||
Word Size | 64 bit | ||||||||||
Cores | 2 | ||||||||||
Threads | 4 | ||||||||||
Max Memory | 16 GiB | ||||||||||
Multiprocessing | |||||||||||
Max SMP | 1-Way (Uniprocessor) | ||||||||||
Electrical | |||||||||||
Power (idle) | 3.1 W | ||||||||||
Vcore | 0.3 V-1.52 V | ||||||||||
TDP | 35 W | ||||||||||
Tjunction | 0 °C – 100 °C | ||||||||||
Tstorage | -25 °C – 125 °C | ||||||||||
Packaging | |||||||||||
| |||||||||||
|
Core i5-2410M is a dual-core mid-range performance mobile x86 microprocessor introduced by Intel in early 2011. This chip, which is fabricated on a 32 nm process based on the Sandy Bridge microarchitecture, operates at 2.3 GHz with a TDP of 35 Watts and a Turbo Boost frequency of up to 2.9 GHz. The i5-2410M incorporates HD Graphics 3000 integrated graphics operating at 650 MHz with a burst frequency of 1.2 GHz and supports up to 16 GiB of dual-channel DDR3-1333 memory.
Cache[edit]
- Main article: Sandy Bridge § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
|||||||||||||||||||||||||||||||||||||
|
Memory controller[edit]
Integrated Memory Controller
|
||||||||||||||
|
Expansions[edit]
Expansion Options |
|||||
|
Wireless[edit]
Wireless Communications | ||||
Cellular | ||||
4G |
|
---|
Graphics[edit]
Integrated Graphics Information
|
||||||||||||||||||||||||||||||||||||||||||||||||||
|
[Edit] Sandy Bridge (Gen6) Hardware Accelerated Video Capabilities | |||||||
---|---|---|---|---|---|---|---|
Codec | Encode | Decode | |||||
Profiles | Levels | Max Resolution | Profiles | Levels | Max Resolution | ||
MPEG-2 (H.262) | ✘ | Main | Main, High | Up to 80 Mbps | |||
MPEG-4 AVC (H.264) | Main | 4.1 | Up to 40 Mbps | Main, High | 4.1 | Up to 40 Mbps | |
VC-1 | ✘ | Advanced, Main, Simple | 3, High, Simple | Up to 40 Mbps |
Features[edit]
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
Facts about "Core i5-2410M - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Core i5-2410M - Intel#pcie + |
device id | 0x116 + |
has 4g support | true + |
has advanced vector extensions | true + |
has ecc memory support | false + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Enhanced SpeedStep Technology +, Intel VT-x +, Extended Page Tables +, Flex Memory Access +, My WiFi Technology + and Identity Protection Technology + |
has intel enhanced speedstep technology | true + |
has intel flex memory access support | true + |
has intel identity protection technology support | true + |
has intel my wifi technology support | true + |
has intel vt-x technology | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has wimax support | true + |
has x86 advanced encryption standard instruction set extension | true + |
integrated gpu | HD Graphics 3000 + |
integrated gpu base frequency | 650 MHz (0.65 GHz, 650,000 KHz) + |
integrated gpu designer | Intel + |
integrated gpu execution units | 12 + |
integrated gpu max frequency | 1,200 MHz (1.2 GHz, 1,200,000 KHz) + |
l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
l3$ description | 12-way set associative + |
l3$ size | 3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) + |
max memory bandwidth | 19.87 GiB/s (20,346.88 MiB/s, 21.335 GB/s, 21,335.25 MB/s, 0.0194 TiB/s, 0.0213 TB/s) + |
max memory channels | 2 + |
supported memory type | DDR3-1333 + and DDR3-1066 + |