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Difference between revisions of "intel/atom/c3808"
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{{intel title|Atom C3808}}
 
{{intel title|Atom C3808}}
−
{{mpu
+
{{chip
 
|name=Atom C3808
 
|name=Atom C3808
−
|no image=Yes
+
|image=denverton (front).png
 
|designer=Intel
 
|designer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
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|core name=Denverton
 
|core name=Denverton
 
|core family=6
 
|core family=6
 +
|core model=95
 
|core stepping=B1
 
|core stepping=B1
 
|process=14 nm
 
|process=14 nm
Line 38: Line 39:
 
|tstorage min=-25 °C
 
|tstorage min=-25 °C
 
|tstorage max=125 °C
 
|tstorage max=125 °C
 +
|tambient min=-40 °C
 +
|tambient max=85 °C
 
|package module 1={{packages/intel/fcbga-1310}}
 
|package module 1={{packages/intel/fcbga-1310}}
 
}}
 
}}
 +
'''Atom C3808''' is a {{arch|64}} [[dodeca-core]] ultra-low power [[x86]] microserver [[system on a chip]] introduced by [[Intel]] in 2017. The C3808, which is manufactured on a [[14 nm process]], is based on the {{intel|Goldmont|l=arch}} microarchitecture. This chip operates at 2 GHz with a [[TDP]] of 25 W. The C3808 supports up to 256 GiB of dual-channel DDR4-2133 [[ECC]] memory. This model is part of {{intel|Denverton|l=core}}'s [[part of::Internet of Things and eTEMP SKUs]] which come with integrated {{intel|QuickAssist Technology}} and support extended ambient operating temperature (-40 °C to 85 °C).
 +
 +
== Cache ==
 +
{{main|intel/microarchitectures/goldmont#Memory_Hierarchy|l1=Goldmont § Cache}}
 +
{{cache size
 +
|l1 cache=672 KiB
 +
|l1i cache=384 KiB
 +
|l1i break=12x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1i policy=write-back
 +
|l1d cache=288 KiB
 +
|l1d break=12x24 KiB
 +
|l1d desc=6-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=12 MiB
 +
|l2 break=6x2 MiB
 +
|l2 desc=16-way set associative
 +
|l2 policy=write-back
 +
}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR3L-1600
 +
|type 2=DDR4-2133
 +
|ecc=Yes
 +
|max mem=256 GiB
 +
|controllers=1
 +
|channels=2
 +
|max bandwidth=31.79 GiB/s
 +
|bandwidth schan=15.89 GiB/s
 +
|bandwidth dchan=31.79 GiB/s
 +
}}
 +
 +
== Expansions ==
 +
This chip incorporates 20 high-speed I/O (HSIO) lanes that may be configured as any combination of the following:
 +
{{expansions main
 +
|
 +
{{expansions entry
 +
|type=PCIe
 +
|pcie revision=3.0
 +
|pcie lanes=16
 +
|pcie config=x8
 +
|pcie config 2=x4
 +
|pcie config 3=x2
 +
|pcie config 4=x1
 +
}}
 +
{{expansions entry
 +
|type=USB
 +
|usb revision=3.0
 +
|usb ports=8
 +
}}
 +
{{expansions entry
 +
|type=SATA
 +
|sata revision=3.0
 +
|sata ports=16
 +
}}
 +
{{expansions entry
 +
|type=HSIO
 +
|hsio lanes=20
 +
}}
 +
}}
 +
 +
== Networking ==
 +
{{network
 +
|eth opts=Yes
 +
|10ge=Yes
 +
|10ge ports=4
 +
}}
 +
 +
== Features ==
 +
{{x86 features
 +
|real=Yes
 +
|protected=Yes
 +
|smm=Yes
 +
|fpu=Yes
 +
|x8616=Yes
 +
|x8632=Yes
 +
|x8664=Yes
 +
|nx=Yes
 +
|mmx=Yes
 +
|emmx=Yes
 +
|sse=Yes
 +
|sse2=Yes
 +
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=Yes
 +
|sse42=Yes
 +
|sse4a=No
 +
|avx=No
 +
|avx2=No
 +
|avx512f=No
 +
|avx512cd=No
 +
|avx512er=No
 +
|avx512pf=No
 +
|avx512bw=No
 +
|avx512dq=No
 +
|avx512vl=No
 +
|avx512ifma=No
 +
|avx512vbmi=No
 +
|avx5124fmaps=No
 +
|avx5124vnniw=No
 +
|avx512vpopcntdq=No
 +
|abm=No
 +
|tbm=No
 +
|bmi1=No
 +
|bmi2=No
 +
|fma3=No
 +
|fma4=No
 +
|aes=Yes
 +
|rdrand=Yes
 +
|sha=Yes
 +
|xop=No
 +
|adx=No
 +
|clmul=No
 +
|f16c=No
 +
|tbt1=No
 +
|tbt2=No
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=Yes
 +
|sst=No
 +
|flex=No
 +
|fastmem=No
 +
|ivmd=No
 +
|intelnodecontroller=No
 +
|intelnode=No
 +
|kpt=No
 +
|ptt=No
 +
|intelrunsure=No
 +
|mbe=No
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=No
 +
|txt=No
 +
|ht=No
 +
|vpro=No
 +
|vtx=Yes
 +
|vtd=Yes
 +
|ept=Yes
 +
|mpx=Yes
 +
|sgx=No
 +
|securekey=No
 +
|osguard=No
 +
|intqat=Yes
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 +
}}
 +
 +
* Intel's Integrated {{intel|QuickAssist Technology}} supports a rate of up to 20 Gbps.

Latest revision as of 00:12, 15 August 2019

Edit Values
Atom C3808
denverton (front).png
General Info
DesignerIntel
ManufacturerIntel
Model NumberC3808
Part NumberHW8076502639702
S-SpecSR38C
MarketServer, Embedded
IntroductionAugust 15, 2017 (announced)
August 15, 2017 (launched)
Release Price$369.00
ShopAmazon
General Specs
FamilyAtom
Series3000
LockedYes
Frequency2,000 MHz
Clock multiplier22
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureGoldmont
Core NameDenverton
Core Family6
Core Model95
Core SteppingB1
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores12
Threads12
Max Memory256 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP25 W
Tjunction0 °C – 100 °C
Tcase0 °C – 86 °C
Tstorage-25 °C – 125 °C
Tambient-40 °C – 85 °C
Packaging
PackageFCBGA-1310 (BGA)
Dimension34 mm x 28 mm
Ball Count1310
Ball CompSAC405
InterconnectBGA-1310

Atom C3808 is a 64-bit dodeca-core ultra-low power x86 microserver system on a chip introduced by Intel in 2017. The C3808, which is manufactured on a 14 nm process, is based on the Goldmont microarchitecture. This chip operates at 2 GHz with a TDP of 25 W. The C3808 supports up to 256 GiB of dual-channel DDR4-2133 ECC memory. This model is part of Denverton's Internet of Things and eTEMP SKUs which come with integrated QuickAssist Technology and support extended ambient operating temperature (-40 °C to 85 °C).

Cache[edit]

Main article: Goldmont § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$672 KiB
688,128 B
0.656 MiB
L1I$384 KiB
393,216 B
0.375 MiB
12x32 KiB8-way set associativewrite-back
L1D$288 KiB
294,912 B
0.281 MiB
12x24 KiB6-way set associativewrite-back
L2$12 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
  6x2 MiB16-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3L-1600, DDR4-2133
Supports ECCYes
Max Mem256 GiB
Controllers1
Channels2
Max Bandwidth31.79 GiB/s
32,552.96 MiB/s
34.134 GB/s
34,134.253 MB/s
0.031 TiB/s
0.0341 TB/s
Bandwidth
Single 15.89 GiB/s
Double 31.79 GiB/s

Expansions[edit]

This chip incorporates 20 high-speed I/O (HSIO) lanes that may be configured as any combination of the following:

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 16
Configuration: x8, x4, x2, x1
USBRevision: 3.0
Max Ports: 8
SATARevision: 3.0
Max Ports: 16
HSIOMax Lanes: 20


Networking[edit]

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
Ethernet
10GbEYes (Ports: 4)

Features[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/atom/c3808&oldid=93384"
Facts about "Atom C3808 - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Atom C3808 - Intel#package + and Atom C3808 - Intel#pcie +
base frequency2,000 MHz (2 GHz, 2,000,000 kHz) +
clock multiplier22 +
core count12 +
core family6 +
core model95 +
core nameDenverton +
core steppingB1 +
designerIntel +
familyAtom +
first announcedAugust 15, 2017 +
first launchedAugust 15, 2017 +
full page nameintel/atom/c3808 +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology +, Intel VT-x +, Intel VT-d +, Integrated QuickAssist Technology +, Extended Page Tables + and Memory Protection Extensions +
has integrated intel quickassist technologytrue +
has intel enhanced speedstep technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size672 KiB (688,128 B, 0.656 MiB) +
l1d$ description6-way set associative +
l1d$ size288 KiB (294,912 B, 0.281 MiB) +
l1i$ description8-way set associative +
l1i$ size384 KiB (393,216 B, 0.375 MiB) +
l2$ description16-way set associative +
l2$ size12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) +
ldateAugust 15, 2017 +
main imageFile:denverton (front).png +
manufacturerIntel +
market segmentServer + and Embedded +
max ambient temperature358.15 K (85 °C, 185 °F, 644.67 °R) +
max case temperature359.15 K (86 °C, 186.8 °F, 646.47 °R) +
max cpu count1 +
max hsio lanes20 +
max junction temperature373.15 K (100 °C, 212 °F, 671.67 °R) +
max memory262,144 MiB (268,435,456 KiB, 274,877,906,944 B, 256 GiB, 0.25 TiB) +
max memory bandwidth31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) +
max memory channels2 +
max sata ports16 +
max storage temperature398.15 K (125 °C, 257 °F, 716.67 °R) +
max usb ports8 +
microarchitectureGoldmont +
min ambient temperature233.15 K (-40 °C, -40 °F, 419.67 °R) +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min junction temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature248.15 K (-25 °C, -13 °F, 446.67 °R) +
model numberC3808 +
nameAtom C3808 +
packageFCBGA-1310 +
part numberHW8076502639702 +
part ofInternet of Things and eTEMP SKUs +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 369.00 (€ 332.10, £ 298.89, ¥ 38,128.77) +
s-specSR38C +
series3000 +
smp max ways1 +
supported memory typeDDR3L-1600 + and DDR4-2133 +
tdp25 W (25,000 mW, 0.0335 hp, 0.025 kW) +
technologyCMOS +
thread count12 +
word size64 bit (8 octets, 16 nibbles) +
x86/has memory protection extensionstrue +