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{{renesas title|R-Car M2}}
 
{{renesas title|R-Car M2}}
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{{mpu}}
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{{chip
 +
|name=R-Car M2
 +
|image=r-car m2.jpg
 +
|designer=Renesas
 +
|designer 2=ARM Holdings
 +
|manufacturer=TSMC
 +
|model number=M2
 +
|part number=R8A7791
 +
|market=Embedded
 +
|first announced=September 26, 2013
 +
|first launched=June, 2015
 +
|family=R-Car
 +
|series=2nd Gen
 +
|frequency=1,500 MHz
 +
|isa=ARMv7
 +
|isa family=ARM
 +
|isa 2=SuperH
 +
|isa 2 family=SuperH
 +
|microarch=Cortex-A15
 +
|microarch 2=SH-4A
 +
|core name=Cortex-A15
 +
|core name 2=SH-4A
 +
|process=28 nm
 +
|technology=CMOS
 +
|word size=32 bit
 +
|core count=3
 +
|thread count=3
 +
|max cpus=1
 +
|v core=1.03 V
 +
|v io=1.8 V
 +
|v io 2=3.3 V
 +
|package module 1={{packages/renesas/fcbga-831}}
 +
}}
 +
'''R-Car M2''' is a mid-range performance embedded [[tri-core]] SoC designed by [[Renesas]] for the automotive industry and introduced in late 2013. The M2 incorporates two {{armh|Cortex-A15}} cores operating at 1.5 GHz and a third {{renesas|SH-4A}} core for real-time processing. This chip incorporates [[imagination technologies|Imagination]]'s {{imgtec|PowerVR SGX544}} [[GPU]] operating at 520 MHz and supports up to dual-channel DDR3-1600 memory.
 +
 
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== Cache ==
 +
{{main|arm holdings/microarchitectures/cortex-a15#Memory_Hierarchy|l1=Cortex-A15 § Cache}}
 +
{{cache size
 +
|l1 cache=192 KiB
 +
|l1i cache=96 KiB
 +
|l1i break=3x32 KiB
 +
|l1d cache=96 KiB
 +
|l1d break=3x32 KiB
 +
|l2 cache=2 MiB
 +
|l2 break=1x2 MiB
 +
}}
 +
 
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR3-1600
 +
|ecc=No
 +
|controllers=1
 +
|channels=2
 +
|width=32 bit
 +
|max bandwidth=11.92 GiB/s
 +
|bandwidth schan=5.96 GiB/s
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|bandwidth dchan=11.92 GiB/s
 +
}}
 +
 
 +
== Expansions ==
 +
* Flash ROM and SRAM, Data bus width: 8 or 16 bits
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* PCI Express2.0 (1 lane)
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* USB 3.0 host interface × 1 port (wPHY)
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* USB 2.0 host interface × 2 ports (wPHY)
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* SD host interface × 3 ch (SDXC, UHS-I)
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* Multimedia card interface × 1 ch
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* Serial ATA interface × 2 ch
 +
* I²C bus interface × 9 ch
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* Serial communication interface (SCIF) × 18 ch
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* Quad serial peripheral interface (QSPI) × 1 ch (for boot)
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* Clock-synchronized serial interface (MSIOF) × 3 ch (SPI/IIS)
 +
* Ethernet AVB controller (IEEE802.1BA/802.1AS/802.1Qav/IEEE1722, GMII/MII, without PHY)
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* Ethernet controller (IEEE802.3u, RMII, without PHY)
 +
 
 +
== Graphics ==
 +
{{integrated graphics
 +
| gpu                = PowerVR SGX544
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| designer            = Imagination Technologies
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| execution units    = 2
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| max displays        = 2
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| frequency          = 520 MHz
 +
}}
 +
 
 +
== Features ==
 +
{{arm features
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|thumb=No
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|thumb2=Yes
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|thumbee=Yes
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|vfpv1=No
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|vfpv2=No
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|vfpv3=No
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|vfpv3-d16=No
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|vfpv3-f16=No
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|vfpv4=Yes
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|vfpv4-d16=No
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|vfpv5=No
 +
|neon=Yes
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|jazelle=No
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|wmmx=No
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|wmmx2=No
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}}
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 +
== Block Diagram ==
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::[[File:r-car m2 block.png|750px]]
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== Dev Board ("KOELSCH") ==
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[[File:R-Car M2 dev board.png|right|200px]]
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* 210 mm x 180 mm
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* R-Car M2
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* 68 MiB serial flash memory
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* 2 GiB DDR3-DRAM-1600; 2x 32-bit configuration
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* RS-232C, UART, USB, SD, LAN, SATA, PCIe, CAN, MLB interfaces (partially via connector)
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* HDMI and LVDS display-out
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* switches, LEDs, I/O expansion headers

Latest revision as of 15:32, 13 December 2017

Edit Values
R-Car M2
r-car m2.jpg
General Info
DesignerRenesas,
ARM Holdings
ManufacturerTSMC
Model NumberM2
Part NumberR8A7791
MarketEmbedded
IntroductionSeptember 26, 2013 (announced)
June, 2015 (launched)
General Specs
FamilyR-Car
Series2nd Gen
Frequency1,500 MHz
Microarchitecture
ISAARMv7 (ARM), SuperH (SuperH)
MicroarchitectureCortex-A15, SH-4A
Core NameCortex-A15, SH-4A
Process28 nm
TechnologyCMOS
Word Size32 bit
Cores3
Threads3
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Vcore1.03 V
VI/O1.8 V, 3.3 V
Packaging
PackageFCBGA-831 (BGA)
Dimension27 mm x 27 mm
Pitch0.80 mm
Ball Count831
InterconnectBGA-831

R-Car M2 is a mid-range performance embedded tri-core SoC designed by Renesas for the automotive industry and introduced in late 2013. The M2 incorporates two Cortex-A15 cores operating at 1.5 GHz and a third SH-4A core for real-time processing. This chip incorporates Imagination's PowerVR SGX544 GPU operating at 520 MHz and supports up to dual-channel DDR3-1600 memory.

Cache[edit]

Main article: Cortex-A15 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$192 KiB
196,608 B
0.188 MiB
L1I$96 KiB
98,304 B
0.0938 MiB
3x32 KiB  
L1D$96 KiB
98,304 B
0.0938 MiB
3x32 KiB  
L2$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  1x2 MiB  

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-1600
Supports ECCNo
Controllers1
Channels2
Width32 bit
Max Bandwidth11.92 GiB/s
12,206.08 MiB/s
12.799 GB/s
12,799.003 MB/s
0.0116 TiB/s
0.0128 TB/s
Bandwidth
Single 5.96 GiB/s
Double 11.92 GiB/s

Expansions[edit]

  • Flash ROM and SRAM, Data bus width: 8 or 16 bits
  • PCI Express2.0 (1 lane)
  • USB 3.0 host interface × 1 port (wPHY)
  • USB 2.0 host interface × 2 ports (wPHY)
  • SD host interface × 3 ch (SDXC, UHS-I)
  • Multimedia card interface × 1 ch
  • Serial ATA interface × 2 ch
  • I²C bus interface × 9 ch
  • Serial communication interface (SCIF) × 18 ch
  • Quad serial peripheral interface (QSPI) × 1 ch (for boot)
  • Clock-synchronized serial interface (MSIOF) × 3 ch (SPI/IIS)
  • Ethernet AVB controller (IEEE802.1BA/802.1AS/802.1Qav/IEEE1722, GMII/MII, without PHY)
  • Ethernet controller (IEEE802.3u, RMII, without PHY)

Graphics[edit]

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUPowerVR SGX544
DesignerImagination Technologies
Execution Units2Max Displays2
Frequency520 MHz
0.52 GHz
520,000 KHz

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
Thumb-2Thumb-2 Extension
ThumbEEThumb Execution Environment Extension
VFPv4Vector Floating Point (VFP) v4 Extension
NEONAdvanced SIMD extension

Block Diagram[edit]

r-car m2 block.png

Dev Board ("KOELSCH")[edit]

R-Car M2 dev board.png
  • 210 mm x 180 mm
  • R-Car M2
  • 68 MiB serial flash memory
  • 2 GiB DDR3-DRAM-1600; 2x 32-bit configuration
  • RS-232C, UART, USB, SD, LAN, SATA, PCIe, CAN, MLB interfaces (partially via connector)
  • HDMI and LVDS display-out
  • switches, LEDs, I/O expansion headers
Retrieved from "https://en.wikichip.org/w/index.php?title=renesas/r-car/m2&oldid=71198"
Facts about "R-Car M2 - Renesas"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
R-Car M2 - Renesas#package +
base frequency1,500 MHz (1.5 GHz, 1,500,000 kHz) +
core count3 +
core nameCortex-A15 + and SH-4A +
core voltage1.03 V (10.3 dV, 103 cV, 1,030 mV) +
designerRenesas + and ARM Holdings +
familyR-Car +
first announcedSeptember 26, 2013 +
first launchedJune 2015 +
full page namerenesas/r-car/m2 +
has ecc memory supportfalse +
instance ofmicroprocessor +
integrated gpuPowerVR SGX544 +
integrated gpu base frequency520 MHz (0.52 GHz, 520,000 KHz) +
integrated gpu designerImagination Technologies +
integrated gpu execution units2 +
io voltage1.8 V (18 dV, 180 cV, 1,800 mV) + and 3.3 V (33 dV, 330 cV, 3,300 mV) +
isaARMv7 + and SuperH +
isa familyARM + and SuperH +
l1$ size192 KiB (196,608 B, 0.188 MiB) +
l1d$ size96 KiB (98,304 B, 0.0938 MiB) +
l1i$ size96 KiB (98,304 B, 0.0938 MiB) +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
ldateJune 2015 +
main imageFile:r-car m2.jpg +
manufacturerTSMC +
market segmentEmbedded +
max cpu count1 +
max memory bandwidth11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels2 +
microarchitectureCortex-A15 + and SH-4A +
model numberM2 +
nameR-Car M2 +
packageFCBGA-831 +
part numberR8A7791 +
process28 nm (0.028 μm, 2.8e-5 mm) +
series2nd Gen +
smp max ways1 +
supported memory typeDDR3-1600 +
technologyCMOS +
thread count3 +
word size32 bit (4 octets, 8 nibbles) +