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{{renesas title|R-Car H2}}
 
{{renesas title|R-Car H2}}
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{{mpu}}
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{{chip
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|name=R-Car H2
 +
|image=r-car h2.jpg
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|designer=Renesas
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|designer 2=ARM Holdings
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|manufacturer=TSMC
 +
|model number=H2
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|part number=R8A7790
 +
|market=Embedded
 +
|first announced=March 25, 2013
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|first launched=June, 2014
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|family=R-Car
 +
|series=2nd Gen
 +
|frequency=1,500 MHz
 +
|frequency 2=1,000 MHz
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|frequency 3=780 MHz
 +
|isa=ARMv7
 +
|isa family=ARM
 +
|isa 2=SuperH
 +
|isa 2 family=SuperH
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|microarch=Cortex A15
 +
|microarch 2=Cortex A7
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|microarch 3=SH-4A
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|core name=Cortex A15
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|core name 2=Cortex A7
 +
|core name 3=SH-4A
 +
|process=28 nm
 +
|technology=CMOS
 +
|word size=32 bit
 +
|core count=9
 +
|thread count=9
 +
|max cpus=1
 +
|v core=1.0 V
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|v io=3.3
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|v io 2=1.8
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|package module 1={{packages/renesas/fcbga-831}}
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}}
 +
'''R-Car H2''' is a high-end embedded [[nona-core]] SoC for the automotive industry introduced by [[Renesas]] in early [[2013]]. The H2 incorporates four {{armh|Cortex-A15}} cores operating at 1.5 GHz, four {{armh|Cortex-A7}} cores operating at 1 GHz, and one {{renesas|SH-4A}} core operating at 780 MHz for real-time processing. This SoC incorporates [[Imagination Technologies|Imagination]]'s {{imgtec|PowerVR G6400}} [[GPU]] operating at 550 MHz and supports up to dual-channel DDR3-1600 memory.
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== Cache ==
 +
{{main|arm holdings/microarchitectures/cortex-a15#Memory_Hierarchy|arm holdings/microarchitectures/cortex-a7#Memory_Hierarchy|l1=Cortex-A15 § Cache|l2=Cortex-A7 § Cache}}
 +
{{cache size
 +
|l1 cache=576 KiB
 +
|l1i cache=288 KiB
 +
|l1i break=9x32 KiB
 +
|l1d cache=288 KiB
 +
|l1d break=9x32 KiB
 +
|l2 cache=2.5 MiB
 +
}}
 +
 
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR3-1600
 +
|ecc=No
 +
|controllers=1
 +
|channels=2
 +
|width=32 bit
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|max bandwidth=11.92 GiB/s
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|bandwidth schan=5.96 GiB/s
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|bandwidth dchan=11.92 GiB/s
 +
}}
 +
 
 +
== Expansions ==
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* Flash ROM and SRAM, Data bus width: 8 or 16 bits
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* PCI Express2.0 (1 lane)
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* USB 3.0 Host interface × 1 port (wPHY)
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* USB 2.0 Host interface × 3 port (wPHY)
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* SD Host interface × 4 ch (SDXC, UHS-I)
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* Multimedia card interface × 2 ch
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* Serial ATA interface × 2 ch
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* I²C bus interface × 8 ch
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* Serial communication interface (SCIF) × 10 ch
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* Quad serial peripheral interface (QSPI) × 1 ch (for boot)
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* Clock-synchronized serial interface (MSIOF) × 4 ch (SPI/IIS)
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* Ethernet controller (IEEE802.3u, RMII, without PHY)
 +
 
 +
== Graphics ==
 +
{{integrated graphics
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| gpu                = PowerVR G6400
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| designer            = Imagination Technologies
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| execution units    = 1
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| max displays        = 2
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| frequency          = 550 MHz
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}}
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== Features ==
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{{arm features
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|thumb=No
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|thumb2=Yes
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|thumbee=Yes
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|vfpv1=No
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|vfpv2=No
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|vfpv3=No
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|vfpv3-d16=No
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|vfpv3-f16=No
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|vfpv4=Yes
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|vfpv4-d16=No
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|vfpv5=No
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|neon=Yes
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|jazelle=No
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|wmmx=No
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|wmmx2=No
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}}
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== Block Diagram ==
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::[[File:r-car h2 block.png|750px]]
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== Dev Board ("LAGER") ==
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[[File:R-Car H2 dev board.png|right|200px]]
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* 210 mm x 180 mm
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* R-Car H2
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* 68 MiB serial flash memory
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* 4 GiB DDR3-DRAM-1600; 1x 64-bit configuration
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* RS-232C, UART, USB, SD, LAN, SATA, PCIe , CAN and MLB interfaces (partially via connector)
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* HDMI and LVDS display-out
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* switches, LEDs, I/O expansion header

Latest revision as of 15:32, 13 December 2017

Edit Values
R-Car H2
r-car h2.jpg
General Info
DesignerRenesas,
ARM Holdings
ManufacturerTSMC
Model NumberH2
Part NumberR8A7790
MarketEmbedded
IntroductionMarch 25, 2013 (announced)
June, 2014 (launched)
General Specs
FamilyR-Car
Series2nd Gen
Frequency1,500 MHz, 1,000 MHz, 780 MHz
Microarchitecture
ISAARMv7 (ARM), SuperH (SuperH)
MicroarchitectureCortex A15, Cortex A7, SH-4A
Core NameCortex A15, Cortex A7, SH-4A
Process28 nm
TechnologyCMOS
Word Size32 bit
Cores9
Threads9
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Vcore1.0 V
VI/O3.3, 1.8
Packaging
PackageFCBGA-831 (BGA)
Dimension27 mm x 27 mm
Pitch0.80 mm
Ball Count831
InterconnectBGA-831

R-Car H2 is a high-end embedded nona-core SoC for the automotive industry introduced by Renesas in early 2013. The H2 incorporates four Cortex-A15 cores operating at 1.5 GHz, four Cortex-A7 cores operating at 1 GHz, and one SH-4A core operating at 780 MHz for real-time processing. This SoC incorporates Imagination's PowerVR G6400 GPU operating at 550 MHz and supports up to dual-channel DDR3-1600 memory.

Cache[edit]

Main articles: Cortex-A15 § Cache and Cortex-A7 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$576 KiB
589,824 B
0.563 MiB
L1I$288 KiB
294,912 B
0.281 MiB
9x32 KiB  
L1D$288 KiB
294,912 B
0.281 MiB
9x32 KiB  
L2$2.5 MiB
2,560 KiB
2,621,440 B
0.00244 GiB
     

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-1600
Supports ECCNo
Controllers1
Channels2
Width32 bit
Max Bandwidth11.92 GiB/s
12,206.08 MiB/s
12.799 GB/s
12,799.003 MB/s
0.0116 TiB/s
0.0128 TB/s
Bandwidth
Single 5.96 GiB/s
Double 11.92 GiB/s

Expansions[edit]

  • Flash ROM and SRAM, Data bus width: 8 or 16 bits
  • PCI Express2.0 (1 lane)
  • USB 3.0 Host interface × 1 port (wPHY)
  • USB 2.0 Host interface × 3 port (wPHY)
  • SD Host interface × 4 ch (SDXC, UHS-I)
  • Multimedia card interface × 2 ch
  • Serial ATA interface × 2 ch
  • I²C bus interface × 8 ch
  • Serial communication interface (SCIF) × 10 ch
  • Quad serial peripheral interface (QSPI) × 1 ch (for boot)
  • Clock-synchronized serial interface (MSIOF) × 4 ch (SPI/IIS)
  • Ethernet controller (IEEE802.3u, RMII, without PHY)

Graphics[edit]

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUPowerVR G6400
DesignerImagination Technologies
Execution Units1Max Displays2
Frequency550 MHz
0.55 GHz
550,000 KHz

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
Thumb-2Thumb-2 Extension
ThumbEEThumb Execution Environment Extension
VFPv4Vector Floating Point (VFP) v4 Extension
NEONAdvanced SIMD extension

Block Diagram[edit]

r-car h2 block.png

Dev Board ("LAGER")[edit]

R-Car H2 dev board.png
  • 210 mm x 180 mm
  • R-Car H2
  • 68 MiB serial flash memory
  • 4 GiB DDR3-DRAM-1600; 1x 64-bit configuration
  • RS-232C, UART, USB, SD, LAN, SATA, PCIe , CAN and MLB interfaces (partially via connector)
  • HDMI and LVDS display-out
  • switches, LEDs, I/O expansion header
Retrieved from "https://en.wikichip.org/w/index.php?title=renesas/r-car/h2&oldid=71192"
Facts about "R-Car H2 - Renesas"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
R-Car H2 - Renesas#package +
base frequency1,500 MHz (1.5 GHz, 1,500,000 kHz) +, 1,000 MHz (1 GHz, 1,000,000 kHz) + and 780 MHz (0.78 GHz, 780,000 kHz) +
core count9 +
core nameCortex A15 +, Cortex A7 + and SH-4A +
core voltage1 V (10 dV, 100 cV, 1,000 mV) +
designerRenesas + and ARM Holdings +
familyR-Car +
first announcedMarch 25, 2013 +
first launchedJune 2014 +
full page namerenesas/r-car/h2 +
has ecc memory supportfalse +
instance ofmicroprocessor +
integrated gpuPowerVR G6400 +
integrated gpu base frequency550 MHz (0.55 GHz, 550,000 KHz) +
integrated gpu designerImagination Technologies +
integrated gpu execution units1 +
io voltage3.3 V (33 dV, 330 cV, 3,300 mV) + and 1.8 V (18 dV, 180 cV, 1,800 mV) +
isaARMv7 + and SuperH +
isa familyARM + and SuperH +
l1$ size576 KiB (589,824 B, 0.563 MiB) +
l1d$ size288 KiB (294,912 B, 0.281 MiB) +
l1i$ size288 KiB (294,912 B, 0.281 MiB) +
l2$ size2.5 MiB (2,560 KiB, 2,621,440 B, 0.00244 GiB) +
ldateJune 2014 +
main imageFile:r-car h2.jpg +
manufacturerTSMC +
market segmentEmbedded +
max cpu count1 +
max memory bandwidth11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels2 +
microarchitectureCortex A15 +, Cortex A7 + and SH-4A +
model numberH2 +
nameR-Car H2 +
packageFCBGA-831 +
part numberR8A7790 +
process28 nm (0.028 μm, 2.8e-5 mm) +
series2nd Gen +
smp max ways1 +
supported memory typeDDR3-1600 +
technologyCMOS +
thread count9 +
word size32 bit (4 octets, 8 nibbles) +