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Difference between revisions of "intel/xeon bronze/3106"
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{{intel title|Xeon Bronze 3106}} | {{intel title|Xeon Bronze 3106}} | ||
− | {{ | + | {{chip |
|name=Xeon Bronze 3106 | |name=Xeon Bronze 3106 | ||
|image=skylake sp (basic).png | |image=skylake sp (basic).png | ||
Line 9: | Line 9: | ||
|part number 2=CD8067303561900 | |part number 2=CD8067303561900 | ||
|s-spec=SR3GL | |s-spec=SR3GL | ||
+ | |s-spec qs=QN0C | ||
|market=Server | |market=Server | ||
|market 2=Workstation | |market 2=Workstation | ||
Line 19: | Line 20: | ||
|frequency=1,700 MHz | |frequency=1,700 MHz | ||
|clock multiplier=17 | |clock multiplier=17 | ||
+ | |cpuid=0x50654 | ||
|isa=x86-64 | |isa=x86-64 | ||
|isa family=x86 | |isa family=x86 | ||
− | |microarch=Skylake | + | |microarch=Skylake (server) |
|platform=Purley | |platform=Purley | ||
|chipset=Lewisburg | |chipset=Lewisburg | ||
Line 32: | Line 34: | ||
|core count=8 | |core count=8 | ||
|thread count=8 | |thread count=8 | ||
+ | |max memory=768 GiB | ||
|max cpus=2 | |max cpus=2 | ||
− | | | + | |smp interconnect=UPI |
+ | |smp interconnect links=2 | ||
+ | |smp interconnect rate=9.6 GT/s | ||
|tdp=85 W | |tdp=85 W | ||
|tcase min=0 °C | |tcase min=0 °C | ||
− | |tcase max= | + | |tcase max=77 °C |
− | |package | + | |dts min=0 °C |
+ | |dts max=89 °C | ||
+ | |package name 1=intel,fclga_3647 | ||
}} | }} | ||
− | '''Xeon Bronze 3106''' is a {{arch|64}} [[octa-core]] [[x86]] dual-socket entry-level server and workstation microprocessor introduced by [[Intel]] in mid-2017. The Bronze 3106, which is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]] sports 1 {{x86|AVX-512}} [[FMA]] unit as well as two {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 1.7 GHz with a TDP of 85 W, supports up 768 GiB of hexa-channel DDR4-2133 ECC memory. | + | '''Xeon Bronze 3106''' is a {{arch|64}} [[octa-core]] [[x86]] dual-socket entry-level server and workstation microprocessor introduced by [[Intel]] in mid-2017. The Bronze 3106, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]] sports 1 {{x86|AVX-512}} [[FMA]] unit as well as two {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 1.7 GHz with a TDP of 85 W, supports up 768 GiB of hexa-channel DDR4-2133 ECC memory. |
== Cache == | == Cache == | ||
− | {{main|intel/microarchitectures/ | + | {{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}} |
{{cache size | {{cache size | ||
|l1 cache=512 KiB | |l1 cache=512 KiB | ||
Line 140: | Line 147: | ||
|fastmem=No | |fastmem=No | ||
|ivmd=Yes | |ivmd=Yes | ||
− | |||
|intelnode=Yes | |intelnode=Yes | ||
|kpt=Yes | |kpt=Yes | ||
|ptt=Yes | |ptt=Yes | ||
− | |||
|mbe=Yes | |mbe=Yes | ||
|isrt=No | |isrt=No | ||
Line 177: | Line 182: | ||
|xfr=No | |xfr=No | ||
}} | }} | ||
+ | |||
+ | == Frequencies == | ||
+ | {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}} | ||
+ | {{frequency table | ||
+ | |freq_base=1,700 MHz | ||
+ | |freq_1=1,700 MHz | ||
+ | |freq_2=1,700 MHz | ||
+ | |freq_3=1,700 MHz | ||
+ | |freq_4=1,700 MHz | ||
+ | |freq_5=1,700 MHz | ||
+ | |freq_6=1,700 MHz | ||
+ | |freq_7=1,700 MHz | ||
+ | |freq_8=1,700 MHz | ||
+ | |freq_avx2_base=1,300 MHz | ||
+ | |freq_avx2_1=1,300 MHz | ||
+ | |freq_avx2_2=1,300 MHz | ||
+ | |freq_avx2_3=1,300 MHz | ||
+ | |freq_avx2_4=1,300 MHz | ||
+ | |freq_avx2_5=1,300 MHz | ||
+ | |freq_avx2_6=1,300 MHz | ||
+ | |freq_avx2_7=1,300 MHz | ||
+ | |freq_avx2_8=1,300 MHz | ||
+ | |freq_avx512_base=800 MHz | ||
+ | |freq_avx512_1=800 MHz | ||
+ | |freq_avx512_2=800 MHz | ||
+ | |freq_avx512_3=800 MHz | ||
+ | |freq_avx512_4=800 MHz | ||
+ | |freq_avx512_5=800 MHz | ||
+ | |freq_avx512_6=800 MHz | ||
+ | |freq_avx512_7=800 MHz | ||
+ | |freq_avx512_8=800 MHz | ||
+ | }} | ||
+ | |||
+ | [[Category:microprocessor models by intel based on skylake low core count die]] |
Latest revision as of 22:23, 28 December 2019
Edit Values | |
Xeon Bronze 3106 | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | 3106 |
Part Number | BX806733106, CD8067303561900 |
S-Spec | SR3GL QN0C (QS) |
Market | Server, Workstation |
Introduction | July 11, 2017 (announced) July 11, 2017 (launched) |
Release Price | $306.00 |
Shop | Amazon |
General Specs | |
Family | Xeon Bronze |
Series | 3000 |
Locked | Yes |
Frequency | 1,700 MHz |
Clock multiplier | 17 |
CPUID | 0x50654 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Skylake (server) |
Platform | Purley |
Chipset | Lewisburg |
Core Name | Skylake SP |
Core Family | 6 |
Core Stepping | U0 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 8 |
Threads | 8 |
Max Memory | 768 GiB |
Multiprocessing | |
Max SMP | 2-Way (Multiprocessor) |
Interconnect | UPI |
Interconnect Links | 2 |
Interconnect Rate | 9.6 GT/s |
Electrical | |
TDP | 85 W |
Tcase | 0 °C – 77 °C |
TDTS | 0 °C – 89 °C |
Packaging | |
Package | FCLGA-3647 (FCLGA) |
Dimension | 76.16 mm × 56.6 mm |
Pitch | 0.8585 mm × 0.9906 mm |
Contacts | 3647 |
Socket | Socket P, LGA-3647 |
Xeon Bronze 3106 is a 64-bit octa-core x86 dual-socket entry-level server and workstation microprocessor introduced by Intel in mid-2017. The Bronze 3106, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm process sports 1 AVX-512 FMA unit as well as two Ultra Path Interconnect links. This microprocessor, which operates at 1.7 GHz with a TDP of 85 W, supports up 768 GiB of hexa-channel DDR4-2133 ECC memory.
Cache[edit]
- Main article: Skylake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Expansions[edit]
Expansion Options
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Features[edit]
[Edit/Modify Supported Features]
Frequencies[edit]
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||||||
---|---|---|---|---|---|---|---|---|---|
1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | ||
Normal | 1,700 MHz | 1,700 MHz | 1,700 MHz | 1,700 MHz | 1,700 MHz | 1,700 MHz | 1,700 MHz | 1,700 MHz | 1,700 MHz |
AVX2 | 1,300 MHz | 1,300 MHz | 1,300 MHz | 1,300 MHz | 1,300 MHz | 1,300 MHz | 1,300 MHz | 1,300 MHz | 1,300 MHz |
AVX512 | 800 MHz | 800 MHz | 800 MHz | 800 MHz | 800 MHz | 800 MHz | 800 MHz | 800 MHz | 800 MHz |
Facts about "Xeon Bronze 3106 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Bronze 3106 - Intel#io + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables + and Transactional Synchronization Extensions + |
has intel enhanced speedstep technology | true + |
has intel speed shift technology | true + |
has intel trusted execution technology | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has second level address translation support | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
l1$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 11 MiB (11,264 KiB, 11,534,336 B, 0.0107 GiB) + |
max memory bandwidth | 95.37 GiB/s (97,658.88 MiB/s, 102.403 GB/s, 102,402.758 MB/s, 0.0931 TiB/s, 0.102 TB/s) + |
max memory channels | 6 + |
max pcie lanes | 48 + |
supported memory type | DDR4-2133 + |