From WikiChip
Difference between revisions of "mediatek/helio/mt6797m"
< mediatek‎ | helio

 
(4 intermediate revisions by 4 users not shown)
Line 1: Line 1:
 
{{mediatek title|Helio X20 M (MT6797M)}}
 
{{mediatek title|Helio X20 M (MT6797M)}}
−
{{mpu
+
{{chip
 
| name                = MediaTek Helio X20 M
 
| name                = MediaTek Helio X20 M
 
| no image            = yes
 
| no image            = yes
Line 108: Line 108:
 
|type=LPDDR3-1866
 
|type=LPDDR3-1866
 
|ecc=No
 
|ecc=No
−
|max mem=4 GiB
+
|max mem=8 GiB
 
|controllers=1
 
|controllers=1
 
|channels=2
 
|channels=2
 
|width=32 bit
 
|width=32 bit
−
|max bandwidth=13.91 GiB/s
+
|max bandwidth=14.93 GB/s (13.90 GiB/s)
−
|bandwidth schan=6.95 GiB/s
+
|bandwidth schan=7.46 GB/s (6.95 GiB/s)
−
|bandwidth dchan=13.91 GiB/s
+
|bandwidth dchan=14.93 GB/s (13.90 GiB/s)
 
}}
 
}}
  

Latest revision as of 01:35, 14 December 2019

Edit Values
MediaTek Helio X20 M
General Info
DesignerMediaTek,
ARM Holdings
ManufacturerTSMC
Model NumberHelio X20 M
Part NumberMT6797M,
MTK6797M
MarketMobile, Embedded
IntroductionMay 12, 2015 (announced)
March 16, 2016 (launched)
General Specs
FamilyHelio
SeriesHelio X
Frequency2,000 MHz, 1,850 MHz, 1,400 MHz
Bus typeAMBA 4 AXI
Microarchitecture
ISAARMv8 (ARM)
MicroarchitectureCortex-A53, Cortex-A72
Core NameCortex-A53, Cortex-A72
Process20 nm
TechnologyCMOS
Word Size64 bit
Cores10
Threads10
Max Memory6 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)

Helio X20 M (MT6797M) is a 64-bit deca-core ARM LTE system on a chip designed by MediaTek and introduced in early 2016. This SoC incorporates 3 independent clusters of cores (called "Tri-Cluster" by MediaTek) operating at varying degrees of performance designed for certain workloads (operating at 1.4 GHz, 1.85 GHz, and 2 GHz) and supports up to 6 GiB of dual-channel LPDDR3-1866 memory. This SoC also incorporates a Mali-T800 MP4 IGP operating at 780 MHz. The chip has a modem supporting LTE User Equipment (UE) category 6.

Architecture[edit]

The Helio X20 is designed is composed of 3 individual clusters of CPU cores depending on the level of performance required by the active applications.

The three clusters are designed as a modified big.LITTLE configuration.

Cache[edit]

Main articles: Cortex-A53 § Cache and Cortex-A72 § Cache
New text document.svg This section is empty; you can help add the missing info by editing this page.

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR3-1866
Supports ECCNo
Max Mem8 GiB
Controllers1
Channels2
Width32 bit
Max Bandwidth14.93 GB/s (13.90 GiB/s)
"GB/s(13.90GiB/s)" is not declared as a valid unit of measurement for this property.
Bandwidth
Single 7.46 GB/s (6.95 GiB/s)
Double 14.93 GB/s (13.90 GiB/s)

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
USB
Revision2.0, 3.0
Ports8
UART
GP I/OYes


Graphics[edit]

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUMali-T880
DesignerARM Holdings
Execution Units4
Frequency780 MHz
0.78 GHz
780,000 KHz
OutputDSI
Max Resolution
DSI2560x1600
Standards
Direct3D11.2
OpenGL3.2
OpenCL1.2
OpenGL ES3.2
OpenVG1.1
Vulkan1.0

Wireless[edit]

Antu network-wireless-connected-100.svgWireless Communications
Wi-Fi
WiFi
802.11acYes
Cellular
2G
CSD Yes
GSM Yes
GPRS Yes
EDGE Yes
3G
UMTS
TD-SCDMAYes
DC-HSDPAYes
HSUPAYes
CDMA2000
1XYes
1xEV-DOYes
4G
LTE Advanced
E-UTRANYes
UE Cat6

Image[edit]

  • Integrated image signal processor supports 32 MP
  • Supports image stabilization
  • Supports video stabilization
  • Supports noise reduction
  • Supports lens shading correction
  • Supports AE/AWB/AF
  • Supports edge enhancement
  • Supports face detection and visual tracking
  • Hardware JPEG encoder

Video[edit]

  • Video encoding 4K2K @ 30fps with H.265 and HDR
  • Video decoding 4K2K @ 30fps, h.264, h.265 / HEVC, MPEG-1/2/4, VC-1, VP-8, VP-9

Audio[edit]

  • Audio content sampling rates 8kHz to 192kHz
  • Audio content sampling format 8-bit/16-bit/24-bit Mono/Stereo
  • I2S, PCM
  • Encode: AMR-NB, AMR-WB, AAC, OGG, ADPCM
  • Decode: WAV, MP3, MP2, AAC, AMR-NB, AMR-WB, MIDI, Vorbis, APE, AAC-plus v1, AAC-plus v2, FLAC, WMA, ADPCM
  • 7.1 channel MHL output

Utilizing devices[edit]

  • Elephone S7
  • Vernee Apollo Lite
Retrieved from "https://en.wikichip.org/w/index.php?title=mediatek/helio/mt6797m&oldid=94843"
Facts about "Helio X20 M (MT6797M) - MediaTek"
RDF feed
base frequency2,000 MHz (2 GHz, 2,000,000 kHz) +, 1,850 MHz (1.85 GHz, 1,850,000 kHz) + and 1,400 MHz (1.4 GHz, 1,400,000 kHz) +
bus typeAMBA 4 AXI +
core count10 +
core nameCortex-A53 + and Cortex-A72 +
designerMediaTek + and ARM Holdings +
familyHelio +
first announcedMay 12, 2015 +
first launchedMarch 16, 2016 +
full page namemediatek/helio/mt6797m +
has 2g supporttrue +
has 3g supporttrue +
has 4g supporttrue +
has cdma2000 1x supporttrue +
has cdma2000 1xev-do supporttrue +
has cdma2000 supporttrue +
has csd supporttrue +
has dc-hsdpa supporttrue +
has e-utran supporttrue +
has ecc memory supportfalse +
has edge supporttrue +
has gprs supporttrue +
has gsm supporttrue +
has hsupa supporttrue +
has lte advanced supporttrue +
has td-scdma supporttrue +
has umts supporttrue +
instance ofmicroprocessor +
integrated gpuMali-T880 +
integrated gpu base frequency780 MHz (0.78 GHz, 780,000 KHz) +
integrated gpu designerARM Holdings +
integrated gpu execution units4 +
isaARMv8 +
isa familyARM +
ldateMarch 16, 2016 +
manufacturerTSMC +
market segmentMobile + and Embedded +
max cpu count1 +
max memory6,144 MiB (6,291,456 KiB, 6,442,450,944 B, 6 GiB, 0.00586 TiB) +
max memory channels2 +
microarchitectureCortex-A53 + and Cortex-A72 +
model numberHelio X20 M +
nameMediaTek Helio X20 M +
part numberMT6797M + and MTK6797M +
process20 nm (0.02 μm, 2.0e-5 mm) +
seriesHelio X +
smp max ways1 +
supported memory typeLPDDR3-1866 +
technologyCMOS +
thread count10 +
used byElephone S7 + and Vernee Apollo Lite +
user equipment category6 +
word size64 bit (8 octets, 16 nibbles) +