Latest revision as of 16:14, 13 December 2017

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Atom Z510
Silverthorne chip
General Info
Designer	Intel
Manufacturer	Intel
Model Number	Z510
Part Number	AC80566UC005DE
S-Spec	SLB2C QENE (QS)
Market	Mobile
Introduction	April 2, 2008 (announced) April 2, 2008 (launched)
Release Price	$45
Shop	Amazon
General Specs
Family	Atom
Series	Z500
Locked	Yes
Frequency	1,100 MHz
Bus type	FSB
Bus speed	100 MHz
Bus rate	400 MT/s
Clock multiplier	11
CPUID	106C2
Microarchitecture
ISA	x86-32 (x86)
Microarchitecture	Bonnell
Platform	Menlow
Chipset	Poulsbo
Core Name	Silverthorne
Core Family	6
Core Model	28
Core Stepping	C0
Process	45 nm
Transistors	47,212,207
Technology	CMOS
Die	24.18 mm² 7.8 mm × 3.1 mm
Word Size	32 bit
Cores	1
Threads	1
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
Power dissipation (average)	220 mW
Power (idle)	100 mW
Vcore	0.75 V-1.1 V
SDP	960 mW
TDP	2 W
Tjunction	0 °C – 90 °C
Tcase	0 °C – 70 °C
Tstorage	-40 °C – 85 °C
Packaging
Package FCBGA-441 (FCBGA) Dimension 13 mm x 14 mm Pin Count 441 Socket BGA-441 (BGA)

Z510 is an ultra-low power 32-bit x86 microprocessor introduced by Intel in early 2008 specifically for Mobile Internet Devices (MID). The Z510, which is based on the Bonnell microarchitecture (Silverthorne core), is manufactured on a 45 nm process. This processor operates at 1.1 Ghz with a TDP of just 2 W and an average power of 220 mW. The MPU features a legacy 400 MT/s front-side bus capable of communicating with the Poulsbo chipset in both low-power CMOS mode as well as normal GTL mode (which also works with other chipsets).

Model price includes the chipset.

Cache[edit]

Main article: Bonnell § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 56 KiB 57,344 B 0.0547 MiB L1I$ 32 KiB 32,768 B 0.0313 MiB 1x32 KiB 8-way set associative   L1D$ 24 KiB 24,576 B 0.0234 MiB 1x24 KiB 6-way set associative write-back L2$ 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB     1x512 KiB 8-way set associative

Memory controller[edit]

This processor has no integrated memory controller.

Graphics[edit]

This processor has no integrated graphics.

Features[edit]

[Edit/Modify Supported Features]

	Supported x86 Extensions & Processor Features
	MMX MMX Extension EMMX Extended MMX Extension SSE Streaming SIMD Extensions SSE2 Streaming SIMD Extensions 2 SSE3 Streaming SIMD Extensions 3 SSSE3 Supplemental SSE3 x86-16 16-bit x86 x86-32 32-bit x86 Real Real Mode Protected Protected Mode SMM System Management Mode FPU Integrated x87 FPU NX No-eXecute EIST Enhanced SpeedStep Technology

Die Shot[edit]

See also: Bonnell § Silverthorne Die

• 45 nm process
• 9 metal layers
• 47,212,207 transistors
• 3.1 mm x 7.8 mm
• 24.18 mm² die size

Documents[edit]

Datasheet[edit]

• Intel Atom Processor Z5xx Series Datasheet, June 2010
• Intel Atom Processor Z5xx Series Datasheet Specification Update, July 2014

Other[edit]

• Atom Z5xx Product Brief, 2008