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'''ARMv2''' is the second [[ARM]] instruction set version which was introduced by [[Acorn]] with the release of the {{acorn|ARM2|l=arch}} in [[1986]]. The ARMv2 was the first instruction set to be used commercially. | '''ARMv2''' is the second [[ARM]] instruction set version which was introduced by [[Acorn]] with the release of the {{acorn|ARM2|l=arch}} in [[1986]]. The ARMv2 was the first instruction set to be used commercially. | ||
== Overview == | == Overview == | ||
The ARMv2 is the second iteration of the ARM instruction set which was introduced with [[Acorn]]'s {{acorn|ARM2|l=arch}} in 1986. The ARMv2 added support for multiplication and a coprocessor communication interface. It also adds two additional status registers for a total of 27 registers. | The ARMv2 is the second iteration of the ARM instruction set which was introduced with [[Acorn]]'s {{acorn|ARM2|l=arch}} in 1986. The ARMv2 added support for multiplication and a coprocessor communication interface. It also adds two additional status registers for a total of 27 registers. | ||
+ | |||
+ | == New Instructions == | ||
+ | ARMv2 adds a number of new instructions: | ||
+ | |||
+ | * [[#movement_instructions|Movement Instructions]] | ||
+ | * [[#load_instructions|Load Instructions]] | ||
+ | * [[#store_instructions|Store Instructions]] | ||
+ | * [[#arithmetic_instructions|Arithmetic Instructions]] | ||
+ | * [[#coprocessor_instructions|Coprocessor Instructions]] | ||
+ | |||
+ | {{isa | ||
+ | | title = New ARMv2 ISA Instructions | ||
+ | | Syntax | ||
+ | | Description | ||
+ | | Action | ||
+ | | cols = 5 | ||
+ | | listing = | ||
+ | {{inst|cols=5|section=<span id="movement_instructions">'''Movement Instructions'''</span><br><small>Movement instructions move data between registers and operands.</small>}} | ||
+ | {{inst|mn=MCR |col 1=MCR<cond> <copro>, <op1>, Rd, Cn, Cm {, <op2>} |col 2=Move to Coprocessor register |col 3 = Coprocessor <copro> = Rd}} | ||
+ | {{inst|mn=MRC |col 1=MRC<cond> <copro>, <op1>, Rd, Cn, Cm , <op2> |col 2=Move register from a Coprocessor |col 3 = Rd = Coprocessor <copro>}} | ||
+ | |||
+ | {{inst|cols=5|section=<span id="load_instructions">'''Load Instructions'''</span><br><small>Load instructions move the content of memory addresses into registers.</small>}} | ||
+ | {{inst|mn=LDC |col 1=LDC<cond>{L} <copro>, Cd, [Rn {, #imm * 4}]{!} |col 2=Load to Coprocessor |col 3 = Coprocessor <copro> = [Rn + imm]<br>If !: Rn = Rn + imm}} | ||
+ | {{inst|mn=LDC |col 1=LDC<cond>{L} <copro>, Cd, [Rn], #{-}<immed8> * 4 |col 2=Load to Coprocessor |col 3 = Coprocessor <copro> = [Rn + imm]<br>Rn = Rn + imm }} | ||
+ | {{inst|mn=LDC |col 1=LDC<cond>{L} <copro>, Cd, [Rn], <option> |col 2=Load to Coprocessor |col 3 = Coprocessor <copro> = [Rn] }} | ||
+ | |||
+ | {{inst|cols=5|section=<span id="store_instructions">'''Store Instructions'''</span><br><small>Store instructions moves the values from registers into memory.</small>}} | ||
+ | {{inst|mn=STC |col 1=STC<cond>{L} <copro>, Cd, [Rn {, #imm * 4}]{!} |col 2=Store from Coprocessor |col 3 = [Rn + imm] = Coprocessor <copro><br>If !: Rn = Rn + imm}} | ||
+ | {{inst|mn=STC |col 1=STC<cond>{L} <copro>, Cd, [Rn], #{-}<immed8> * 4 |col 2=Store from Coprocessor |col 3 = [Rn + imm] = Coprocessor <copro><br>Rn = Rn + imm }} | ||
+ | {{inst|mn=STC |col 1=STC<cond>{L} <copro>, Cd, [Rn], <option> |col 2=Store from Coprocessor |col 3 = [Rn] = Coprocessor <copro> }} | ||
+ | |||
+ | {{inst|cols=5|section=<span id="coprocessor_instructions">'''Coprocessor Instructions'''</span><br><small>Operates on a Coprocessor.</small>}} | ||
+ | {{inst|mn=CDP |col 1=CDP<cond> <copro>, <op1>, Cd, Cn, Cm, <op2> |col 2=Coprocessor Data Process |col 3 = Execut OP Given on Coprocessor <copro>}} | ||
+ | |||
+ | {{inst|cols=5|section=<span id="arithmetic_instructions">'''Arithmetic Instructions'''</span><br><small>Arithmetic instructions perform basic mathematical operations on two operands.</small>}} | ||
+ | {{inst|mn=MLA |col 1=MLA<cond>{S} Rd, Rm, Rs, Rn |col 2=Multiply and accumulate |col 3 =Rd = (Rm * Rs) + Rn}} | ||
+ | {{inst|mn=MUL |col 1=MUL<cond>{S} Rd, Rm, Rs |col 2=Multiply |col 3 =Rd = Rm * Rs}} | ||
+ | }} |
Latest revision as of 19:30, 10 July 2017
ARM ISA | |
General | |
Variants | |
Extensions | |
Topics | |
Versions(all) | |
ARMv2 is the second ARM instruction set version which was introduced by Acorn with the release of the ARM2 in 1986. The ARMv2 was the first instruction set to be used commercially.
Overview[edit]
The ARMv2 is the second iteration of the ARM instruction set which was introduced with Acorn's ARM2 in 1986. The ARMv2 added support for multiplication and a coprocessor communication interface. It also adds two additional status registers for a total of 27 registers.
New Instructions[edit]
ARMv2 adds a number of new instructions:
- Movement Instructions
- Load Instructions
- Store Instructions
- Arithmetic Instructions
- Coprocessor Instructions
New ARMv2 ISA Instructions | ||||
---|---|---|---|---|
Mnemonic | Syntax | Description | Action | |
Movement Instructions Movement instructions move data between registers and operands. | ||||
MCR | MCR<cond> <copro>, <op1>, Rd, Cn, Cm {, <op2>} | Move to Coprocessor register | Coprocessor <copro> = Rd | |
MRC | MRC<cond> <copro>, <op1>, Rd, Cn, Cm , <op2> | Move register from a Coprocessor | Rd = Coprocessor <copro> | |
Load Instructions Load instructions move the content of memory addresses into registers. | ||||
LDC | LDC<cond>{L} <copro>, Cd, [Rn {, #imm * 4}]{!} | Load to Coprocessor | Coprocessor <copro> = [Rn + imm] If !: Rn = Rn + imm | |
LDC | LDC<cond>{L} <copro>, Cd, [Rn], #{-}<immed8> * 4 | Load to Coprocessor | Coprocessor <copro> = [Rn + imm] Rn = Rn + imm | |
LDC | LDC<cond>{L} <copro>, Cd, [Rn], <option> | Load to Coprocessor | Coprocessor <copro> = [Rn] | |
Store Instructions Store instructions moves the values from registers into memory. | ||||
STC | STC<cond>{L} <copro>, Cd, [Rn {, #imm * 4}]{!} | Store from Coprocessor | [Rn + imm] = Coprocessor <copro> If !: Rn = Rn + imm | |
STC | STC<cond>{L} <copro>, Cd, [Rn], #{-}<immed8> * 4 | Store from Coprocessor | [Rn + imm] = Coprocessor <copro> Rn = Rn + imm | |
STC | STC<cond>{L} <copro>, Cd, [Rn], <option> | Store from Coprocessor | [Rn] = Coprocessor <copro> | |
Coprocessor Instructions Operates on a Coprocessor. | ||||
CDP | CDP<cond> <copro>, <op1>, Cd, Cn, Cm, <op2> | Coprocessor Data Process | Execut OP Given on Coprocessor <copro> | |
Arithmetic Instructions Arithmetic instructions perform basic mathematical operations on two operands. | ||||
MLA | MLA<cond>{S} Rd, Rm, Rs, Rn | Multiply and accumulate | Rd = (Rm * Rs) + Rn | |
MUL | MUL<cond>{S} Rd, Rm, Rs | Multiply | Rd = Rm * Rs |