Latest revision as of 16:41, 1 November 2018

Gen9 (Generation 9) is the microarchitecture for Intel's graphics processing unit utilized by Skylake-based microprocessors. Gen9 is the successor to Gen8 used by Broadwell. The Gen9 microarchitecture is designed separately by Intel and then integrated onto the same Skylake SoC die.

Codenames[edit]

Various models support different Graphics Tiers (GT) which provides different levels of performance. Some models also support an additional eDRAM side cache.

Models[edit]

1. ↑ The CPU Stepping is the actual CPU design stepping.
2. ↑ The GT Stepping refers to the GT design stepping.
3. ↑ The Device2 ID is the PCI device ID that identifies the GT SKU for driver software
4. ↑ The GT Device2 Revision ID identifies the silicon stepping for driver software.

Performance[edit]

Hardware Accelerated Video[edit]

Process Technology[edit]

Main article: Broadwell § Process Technology

Gen9 are part of the Skylake SoC die which uses the same 14 nm process used for the Broadwell microarchitecture.

Architecture[edit]

Gen9 presents a large departure from the Gen8 and previous architectures.

Key changes from Gen8[edit]

• Architecture is drastically different
  • Gen9 is composed of 3 truly independent major components: Display block, Unslice, and the Slice.
  • Shared Virtual Memory (SVM) improvements
    • Improved cache coherency performance
• Unslice
  • Now sits on its own power gating/clock domain
    • Capable of running at higher speeds if the situation allows (irrespective of slice clock)
    • Can allow for pure fixed media alone
  • Higher throughput
  • Tessellator AutoStrip
  • Fixed function video encoder in the Quick Sync engine
  • codec (decode&encode) support for HEVC, VP8, MJPEG
  • RAW imaging capabilities
• Slice
  • Floating point atomics (min/max/cmpexch)
  • L3 Cache
    • Increased to 768 KiB/slice (up from 576 KiB/slice)
    • Request queue size was increased
• Subslice
  • Adaptive scalable texture compression (ASTC)
  • 16x multi-sample anti-aliasing (MSAA)
  • Post depth test coverage mask
  • Multi-plane overlays
  • Texture samplers now natively support an NV12 YUV
  • Min/max texture filtering
  • Preemption of execution is now supported at the thread level
  • Round robin scheduling of threads within an execution unit.
  • new native support for the 32-bit float atomics operations of min, max, and compare/exchange.
  • 16-bit floating point capability is improved with native support for denormals and gradual underflow
• L4$
  • The eDRAM is now a side cache instead of an L4$ like it was in Gen8. (See Skylake §eDRAM architectural changes for the reason)
  • Side-cache eDRAM was moved into the system agent adjacent to the display controller

Block Diagram[edit]

Entire SoC Overview[edit]

Gen9[edit]

This block is for the most common setup, which is GT2 with 24 execution units.

Individual Core[edit]

See Skylake#Individual_Core.

Unslice[edit]

The Unslice is one of Gen9's major components and is responsible for the fixed-function geometry capabilities, fixed-function media capabilities, and it provides the interface to the memory fabric. One of the big changes in Gen9 is that the Unslice now sits on its own power/clock domain. This change allows the Unslice to operate at its own speed provided higher on-demand performance when desired. This change has a number of other benefits such as being able to turn off the slices (one or more) when they're not used in cases where pure fixed-function media is used. Additionally, the Unslice is now capable of running at a higher clock while the slice can run at a slower clock when the scenario demands it (such as in cases where higher fixed-function geometry or memory demands occur).

The Command Stream (CS) unit manages the the flow of execution for the FF Pipeline (3D Pipeline) and the Media pipelines. The CS unit performs the switching between pipelines and forwarding command streams to the different stages. Data in the pipeline are passed to the next unit using a messaging network. Messages can be passed directly through registers or by using the URB. The Command Stream also manages the allocation of the URB and supports the Constant URB Entry (CURB) function. The Unified Return Buffer (URB) is globally shared and is explicitly addressed. The pipeline's fixed-function blocks have both read and write access to the URB, additionally the shader cores have write access to the URB.

The media general-purpose pipeline consists of two fixed-function units: Video Front End (VFE) and the Thread Spawner (TS). The VFE unit handles the interfacing with the Command Streamer, writes thread payload data into the Unified Return Buffer, as well as prepares threads to be dispatched through TS unit. The VFE unit also contains the hardware Variable Length Decode (VLD) engine for MPEG-2 video decode. The TS unit is primarily responsible for interfacing with the Thread Dispatcher (TD) unit which is responsible for spawning new root-node parent threads originated from VFE unit and for spawning child threads (either leaf-node child threads or branch-node parent thread).

Fixed-Function[edit]

• Multi-Format Codec (MFX)
  • HEVC Decode
  • Support for HEVC & VP8 in PAK (for encode)
  • New fixed function within MFX for real-time AVC encoding usages

• Video Quality Engine (VQE)
  • 16-bit processing path
  • 5x5 spatial denoise filter
  • Local Adaptive Contrast Enhancement (LACE)
  • Camera processing features to allow high-resolution raw camera processing

• Scalar and Format Conversion (SFC)
  • Allows for inline format conversion & upscaling or downscaling of imagest
  • Can be coupled with decoder to allow high-quality video processing in the FF units in the unslice without utilizing the media sampler in the slices themselves.

3D Pipeline Stages[edit]

Slice[edit]

Slices are a cluster of subslices. For most configurations in Gen9, 3 subslices are aggregated into 1 slice to form a total of 24 execution units (depending on the model, some low end models do have less). The slice incorporates the thread dispatch routine, level 3 cache (L3$), a highly banked shared local memory structure, fixed function logic for atomics and barriers, and a number of fixed-function units for various media capabilities. The Global Thread Dispatcher (GTD) is responsible for load balancing thread distribution across the entire device. The global thread dispatcher works in concert with local thread dispatchers in each subslice.

Execution Unit (EU)[edit]

The Execution Units (EUs) are the programmable shader units - each one is an independent computational unit used for execution of 3D shaders, media, and GPGPU kernels. Internally, each unit is hardware multi-threaded capable of executing multi-issue SIMD operations. Execution is multi-issue per clock to pipelines capable of integer, single and double precision floating point operations, SIMD branch capability, logical operations, transcendental operations, and other miscellaneous operations. Communication between the EUs and the support units (shared function units such as operations involving texture sampling or scatter/gather load/stores) is done via messages that were programmatically constructed. Dependency hardware allows threads to sleep until the requested data is returned from those units.

Shared Functions are hardware units that provide a set of specialized supplemental functionality for the EUs. As their name implies they implement functions with insufficient demand to justify the cost of being implemented in the individual EUs. Functionality in these units are shared among the EUs in the subslice. Communication between the EUs and the Shared Function is done via lightweight message passing. Messages are a small self-contained packet of information created by a kernel and directed to a specific shared function. EU threads awaiting the return of a message from the Shared Function unit go into temporary sleep.

The Execution Unit is composed of 7 threads. Each thread has 128 SIMD-8 32-bit registers in a General-Purpose Register File (GRF) and supporting architecture specific registers (ARF). The EU can co-issue to four instruction processing units, including two FPUs, a branch unit, and a message send unit.

Preemption Granularity[edit]

Preemption in Gen9 was improved over Gen8 in a number of way. Preemption is important for mullti-tasking system and especially important for improving responsiveness of operations (i.e. the ability to stop and start operations quickly with minimal latency interruption for the end user). In Broadwell (Gen8) Intel added support for the ability to stop operations on object-level for 3D workloads such as on a triangle boundary (i.e. beginning of a triangle, between two triangles, between two lines or points) and be able to preempt and restore back to those operations. In Gen9 Intel added the ability to stop execution units on an instruction boundary and be able to restore them (previously such preemption was only possible at the boundary of a kernel - i.e. the entire kernel execution must take places before preemption was possible). Gen9 added support for thread-group (complete kernel execution) to mid-thread (instruction boundary) for compute workloads:

Example of responsiveness (Source: IDF15)

Display[edit]

The display has a memory interface (supporting high memory bandwidth coming directly to the display sub-system), a front-end that is responsible for sorting and sequencing the requests (as well as handling things such as rotated displays), and display pipes. The display pipes perform input format conversion, multi-plane composition, color conversion, and scaling the result. The final part of the display port are the prot encoders that convert the input form the display pipes to the appropriate standard used (DP/HDMI/eDP). A number of improvements in Gen9 in the display block were done with respect to the display pipes, specifically being able to consume lossless compression directly without doing any extra unnecessary conversion operations. Additionally the pipes now support render compressed surfaces, Y-tiled surfaces, and on the fly 90/270 rotations.

Multiple Display Planes in a Pipe[edit]

• Three plane sources + background
  • All 3 are independent
  • Fixed order (highest priority is plane3, lowest is background)
  • Planes can be:
    • YUV video
    • RGB windows/desktop
  • Fixed visual priority/blending order
  • Color correction of result
  • Two 7x5 scalers
    • Bind to individual planes or pipe output
• Intended to support various OS features such as
  • Microsoft's MPO (Multiplane overlay support)
  • Android's SurfaceFlinger

Scalability[edit]

Gen9 can scale from 1 to 3 slices producing SKUs ranging from 12 to 72 execution units (note that the 12 EUs are formed from half a slice effectively).

GT1 (ULP)[edit]

GT1 is the most compact configuration offering two benefits: reduced cost and reduced power. GT1 is made of 1 slice containing 2 subslices with 6 EUs/subslice for a total of 12 EUs. With the scale-down, GT1 changes the ratio to 6:1 EU:sampler ratio. Note that this does retains the same ratio of 12 texels/clock and 8 pixels/clock at the backend. This configuration is better suited for some of the low power workload (e.g. ASTC-LDR+HDR, ETC1/2 compression). Note that software stack remains unchanged compared to the larger models.

GT1.5[edit]

GT1.5, offers 3 subslices of 6 EUs each for a total of 18 EUs.

GT2[edit]

GT2 is the standard configuration consisting of 1 slice with 3 subslices and 8 EU/subslice for a total of 24 EUs.

GT3[edit]

GT3 consists of 2 slices with 3 subslices in each and 8 EU/subslice for a total of 48 EUs.

Halo (GT4)[edit]

Codename Halo (GT4) is the most complex configuration offering the highest execution units count. Halo incorporates 3 slices with 3 subslices/slice and 8 EU/subslice for a total of 72 EUs.

Configuration[edit]

Datasheets[edit]

White Paper[edit]

• The Compute Architecture of Intel Processor Graphics Gen9

Programmer's Reference Manual[edit]

• Volume 1: Preface
• Volume 2a Addendum: Command Reference: Instructions (Command Opcodes) for the HEVC Micro-Controller (HuC)
• Volume 2a: Command Reference: Instructions (Command Opcodes)
• Volume 2c: Command Reference: Registers Part 1 – Registers A through L
• Volume 2c: Command Reference: Registers Part 2 – Registers M through Z
• Volume 2d: Command Reference: Structures
• Volume 3: GPU Overview
• Volume 4: Configurations
• Volume 5: Memory Views
• Volume 6: Command Stream Programming
• Volume 7: 3D-Media-GPGPU
• Volume 8: Media VDBOX
• Volume 9: Media Video Enhancement (VEBOX) Engine
• Volume 10: HEVC Codec Pipeline (HCP)
• Volume 11: Blitter
• Volume 12: Display
• Volume 13: Memory-mapped Input/Output (MMIO)
• Volume 14: Observability
• Volume 15: Scaler Format Converter (SFC)
• Volume 16: Workarounds