From WikiChip
Difference between revisions of "intel/celeron/3855u"
m (Bot: moving all {{mpu}} to {{chip}}) |
|||
(2 intermediate revisions by the same user not shown) | |||
Line 1: | Line 1: | ||
{{intel title|Celeron 3855U}} | {{intel title|Celeron 3855U}} | ||
− | {{ | + | {{chip |
|name=Celeron 3855U | |name=Celeron 3855U | ||
|image=skylake u (front; standard).png | |image=skylake u (front; standard).png | ||
Line 49: | Line 49: | ||
|package module 1={{packages/intel/fcbga-1356}} | |package module 1={{packages/intel/fcbga-1356}} | ||
}} | }} | ||
− | '''Celeron 3855U''' is a {{arch|64}} [[dual-core]] budget [[x86]] mobile microprocessor introduced by [[Intel]] in late [[2015]]. Fabricated on a [[14 nm process]] based on the {{intel|Skylake}} microarchitecture, this processor operates at 1.6 GHz. The 3855U has a TDP of 15 W with a configurable-down | + | '''Celeron 3855U''' is a {{arch|64}} [[dual-core]] budget [[x86]] mobile microprocessor introduced by [[Intel]] in late [[2015]]. Fabricated on a [[14 nm process]] based on the {{intel|Skylake}} microarchitecture, this processor operates at 1.6 GHz. The 3855U has a TDP of 15 W with a configurable TDP-down of 10 W. This chip incorporates the {{intel|HD Graphics 510}} GPU operating at 300 MHz with a burst frequency of 900 MHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory. |
== Cache == | == Cache == | ||
Line 162: | Line 162: | ||
|avx=No | |avx=No | ||
|avx2=No | |avx2=No | ||
− | + | ||
|abm=Yes | |abm=Yes | ||
|tbm=No | |tbm=No |
Latest revision as of 16:15, 13 December 2017
Edit Values | |||||||||||||
Celeron 3855U | |||||||||||||
![]() | |||||||||||||
General Info | |||||||||||||
Designer | Intel | ||||||||||||
Manufacturer | Intel | ||||||||||||
Model Number | 3855U | ||||||||||||
Part Number | FJ8066201931008 | ||||||||||||
S-Spec | SR2EV | ||||||||||||
Market | Mobile | ||||||||||||
Introduction | August 15, 2015 (announced) December 27, 2015 (launched) | ||||||||||||
Release Price | $107.00 | ||||||||||||
Shop | Amazon | ||||||||||||
General Specs | |||||||||||||
Family | Celeron | ||||||||||||
Series | 3000 | ||||||||||||
Locked | Yes | ||||||||||||
Frequency | 1,600 MHz | ||||||||||||
Bus type | OPI | ||||||||||||
Bus rate | 4 GT/s | ||||||||||||
Clock multiplier | 16 | ||||||||||||
Microarchitecture | |||||||||||||
ISA | x86-64 (x86) | ||||||||||||
Microarchitecture | Skylake | ||||||||||||
Core Name | Skylake U | ||||||||||||
Core Family | 6 | ||||||||||||
Core Model | 78 | ||||||||||||
Core Stepping | D1 | ||||||||||||
Process | 14 nm | ||||||||||||
Transistors | 1,750,000,000 | ||||||||||||
Technology | CMOS | ||||||||||||
Die | 98.57 mm² 10.3 mm × 9.57 mm | ||||||||||||
MCP | Yes (2 dies) | ||||||||||||
Word Size | 64 bit | ||||||||||||
Cores | 2 | ||||||||||||
Threads | 2 | ||||||||||||
Max Memory | 32 GiB | ||||||||||||
Multiprocessing | |||||||||||||
Max SMP | 1-Way (Uniprocessor) | ||||||||||||
Electrical | |||||||||||||
Vcore | 0.55 V-1.52 V | ||||||||||||
TDP | 15 W | ||||||||||||
cTDP down | 10 W | ||||||||||||
Tjunction | 0 °C – 100 °C | ||||||||||||
Tstorage | -25 °C – 125 °C | ||||||||||||
Packaging | |||||||||||||
|
Celeron 3855U is a 64-bit dual-core budget x86 mobile microprocessor introduced by Intel in late 2015. Fabricated on a 14 nm process based on the Skylake microarchitecture, this processor operates at 1.6 GHz. The 3855U has a TDP of 15 W with a configurable TDP-down of 10 W. This chip incorporates the HD Graphics 510 GPU operating at 300 MHz with a burst frequency of 900 MHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory.
Cache[edit]
- Main article: Skylake § Cache
![]() |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
||||||||||||||||||||||||||||||||||||
|
Memory controller[edit]
![]() |
Integrated Memory Controller
|
|||||||||||||
|
Expansions[edit]
![]() |
Expansion Options
|
|||||||
|
Graphics[edit]
![]() |
Integrated Graphics Information
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
[Edit] Skylake (Gen9) Hardware Accelerated Video Capabilities | |||||||
---|---|---|---|---|---|---|---|
Codec | Encode | Decode | |||||
Profiles | Levels | Max Resolution | Profiles | Levels | Max Resolution | ||
MPEG-2 (H.262) | Main | High | 1080p (FHD) | Main | Main, High | 1080p (FHD) | |
MPEG-4 AVC (H.264) | High, Main | 5.1 | 2160p (4K) | Main, High, SHP, MHP | 5.1 | 2160p (4K) | |
JPEG/MJPEG | Baseline | - | 16k x 16k | Baseline | Unified | 16k x 16k | |
HEVC (H.265) | Main | 5.1 | 2160p (4K) | Main, Main 10 | 5.1 | 2160p (4K) | |
VC-1 | ✘ | Advanced, Main, Simple | 3, High | 3840x3840 | |||
VP8 | Unified | Unified | - | 0 | Unified | 1080p | |
VP9 | ✘ | 0 | Unified | 2160p (4K) |
Features[edit]
[Edit/Modify Supported Features]
![]() |
Supported x86 Extensions & Processor Features
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
Facts about "Celeron 3855U - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Celeron 3855U - Intel#package + and Celeron 3855U - Intel#io + |
base frequency | 1,600 MHz (1.6 GHz, 1,600,000 kHz) + |
bus rate | 4,000 MT/s (4 GT/s, 4,000,000 kT/s) + |
bus type | OPI + |
clock multiplier | 16 + |
core count | 2 + |
core family | 6 + |
core model | 78 + |
core name | Skylake U + |
core stepping | D1 + |
core voltage (max) | 1.52 V (15.2 dV, 152 cV, 1,520 mV) + |
core voltage (min) | 0.55 V (5.5 dV, 55 cV, 550 mV) + |
designer | Intel + |
device id | 0x1906 + |
die area | 98.57 mm² (0.153 in², 0.986 cm², 98,570,000 µm²) + |
die count | 2 + |
die length | 10.3 mm (1.03 cm, 0.406 in, 10,300 µm) + |
die width | 9.57 mm (0.957 cm, 0.377 in, 9,570 µm) + |
family | Celeron + |
first announced | August 15, 2015 + |
first launched | December 27, 2015 + |
full page name | intel/celeron/3855u + |
has ecc memory support | false + |
has extended page tables support | true + |
has feature | Advanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Software Guard Extensions +, Secure Key Technology +, Flex Memory Access +, Smart Response Technology +, My WiFi Technology + and Identity Protection Technology + |
has intel enhanced speedstep technology | true + |
has intel flex memory access support | true + |
has intel identity protection technology support | true + |
has intel my wifi technology support | true + |
has intel secure key technology | true + |
has intel smart response technology support | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
integrated gpu | HD Graphics 510 + |
integrated gpu base frequency | 300 MHz (0.3 GHz, 300,000 KHz) + |
integrated gpu designer | Intel + |
integrated gpu execution units | 12 + |
integrated gpu max frequency | 900 MHz (0.9 GHz, 900,000 KHz) + |
integrated gpu max memory | 32,768 MiB (33,554,432 KiB, 34,359,738,368 B, 32 GiB) + |
is multi-chip package | true + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
l3$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
ldate | December 27, 2015 + |
main image | ![]() |
manufacturer | Intel + |
market segment | Mobile + |
max cpu count | 1 + |
max junction temperature | 373.15 K (100 °C, 212 °F, 671.67 °R) + |
max memory | 32,768 MiB (33,554,432 KiB, 34,359,738,368 B, 32 GiB, 0.0313 TiB) + |
max memory bandwidth | 31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) + |
max memory channels | 2 + |
max pcie lanes | 10 + |
max storage temperature | 398.15 K (125 °C, 257 °F, 716.67 °R) + |
microarchitecture | Skylake + |
min junction temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
min storage temperature | 248.15 K (-25 °C, -13 °F, 446.67 °R) + |
model number | 3855U + |
name | Celeron 3855U + |
package | FCBGA-1356 + |
part number | FJ8066201931008 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 107.00 (€ 96.30, £ 86.67, ¥ 11,056.31) + |
s-spec | SR2EV + |
series | 3000 + |
smp max ways | 1 + |
supported memory type | DDR4-2133 +, LPDDR3-1866 + and DDR3L-1600 + |
tdp | 15 W (15,000 mW, 0.0201 hp, 0.015 kW) + |
tdp down | 10 W (10,000 mW, 0.0134 hp, 0.01 kW) + |
technology | CMOS + |
thread count | 2 + |
transistor count | 1,750,000,000 + |
word size | 64 bit (8 octets, 16 nibbles) + |
x86/has software guard extensions | true + |