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Difference between revisions of "intel/core i3/i3-6100h"
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{{intel title|Core i3-6100H}}
 
{{intel title|Core i3-6100H}}
−
{{mpu
+
{{chip
−
|name=Intel Core i3-6100H
+
|name=Core i3-6100H
−
|no image=Yes
+
|image=skylake h (front).png
 
|designer=Intel
 
|designer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
Line 10: Line 10:
 
|market=Mobile
 
|market=Mobile
 
|first announced=September 1, 2015
 
|first announced=September 1, 2015
−
|first launched=September 1, 2015
+
|first launched=September 27, 2015
 +
|last order=April 19, 2019
 +
|last shipment=October 18, 2019
 +
|release price=$225
 
|family=Core i3
 
|family=Core i3
−
|series=6100
+
|series=i3-6000
 
|locked=Yes
 
|locked=Yes
−
|frequency=2700 MHz
+
|frequency=2,700 MHz
 
|bus type=DMI 3.0
 
|bus type=DMI 3.0
 +
|bus links=4
 
|bus rate=8 GT/s
 
|bus rate=8 GT/s
 
|clock multiplier=27
 
|clock multiplier=27
Line 26: Line 30:
 
|core stepping=R0
 
|core stepping=R0
 
|process=14 nm
 
|process=14 nm
−
|word size=64 bits
+
|technology=CMOS
 +
|die area=98.57 mm²
 +
|die length=10.3 mm
 +
|die width=9.57 mm
 +
|word size=64 bit
 
|core count=2
 
|core count=2
 
|thread count=4
 
|thread count=4
 
|max cpus=1
 
|max cpus=1
 
|max memory=64 GiB
 
|max memory=64 GiB
 +
|v core min=0.55 V
 +
|v core max=1.52 V
 
|tdp=35 W
 
|tdp=35 W
 
|temp min=0 °C
 
|temp min=0 °C
 
|temp max=100 °C
 
|temp max=100 °C
 +
|tjunc min=0 °C
 +
|tjunc max=100 °C
 +
|tstorage min=-25 °C
 +
|tstorage max=125 °C
 
|package module 1={{packages/intel/fcbga-1440}}
 
|package module 1={{packages/intel/fcbga-1440}}
 
}}
 
}}
−
'''Core i3-6100H''' is a {{arch|64}} [[dual-core]] low-end mobile performance [[microprocessor]] introduced by [[Intel]] late 2015. This processor, which is based on the {{intel|Skylake}} microarchitecture and manufactured in [[14 nm process]], has a base frequency of 2.7 GHz with a TDP of 35 W. This processor incorporates the {{intel|HD Graphics 530}} [[GPU]] clocked at 350 MHz with a max frequency of 900 MHz.
+
'''Core i3-6100H''' is a {{arch|64}} [[dual-core]] [[x86]] low-end mobile [[microprocessor]] introduced by [[Intel]] in late 2015. The i3-6100H, which is based on the {{intel|Skylake|l=arch}} microarchitecture and is fabricated on a [[14 nm process]], has a base frequency of 2.7 GHz with a TDP of 35 W. This processor incorporates the {{intel|HD Graphics 530}} [[integrated graphics]] operating at 350 MHz with a turbo frequency of 900 MHz. This model supports 64 GiB of dual-channel DDR4-2133 memory.
  
 
== Cache ==
 
== Cache ==
 
{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
 
{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
−
{{cache info
+
{{cache size
 +
|l1 cache=128 KiB
 
|l1i cache=64 KiB
 
|l1i cache=64 KiB
 
|l1i break=2x32 KiB
 
|l1i break=2x32 KiB
 
|l1i desc=8-way set associative
 
|l1i desc=8-way set associative
−
|l1i extra=(per core, write-back)
 
 
|l1d cache=64 KiB
 
|l1d cache=64 KiB
 
|l1d break=2x32 KiB
 
|l1d break=2x32 KiB
 
|l1d desc=8-way set associative
 
|l1d desc=8-way set associative
−
|l1d extra=(per core, write-back)
+
|l1d policy=write-back
 
|l2 cache=512 KiB
 
|l2 cache=512 KiB
 
|l2 break=2x256 KiB
 
|l2 break=2x256 KiB
 
|l2 desc=4-way set associative
 
|l2 desc=4-way set associative
−
|l2 extra=(per core, write-back)
+
|l2 policy=write-back
 
|l3 cache=3 MiB
 
|l3 cache=3 MiB
−
|l3 desc=shared
+
|l3 break=2x1.5 MiB
 +
|l3 policy=write-back
 +
}}
 +
 
 +
== Memory controller ==
 +
{{memory controller
 +
|type=LPDDR3-1866
 +
|type 2=DDR3L-1600
 +
|type 3=DDR4-2133
 +
|ecc=No
 +
|max mem=64 GiB
 +
|controllers=1
 +
|channels=2
 +
|max bandwidth=31.79 GiB/s
 +
|bandwidth schan=15.89 GiB/s
 +
|bandwidth dchan=31.79 GiB/s
 +
}}
 +
 
 +
== Expansions ==
 +
{{expansions
 +
| pcie revision      = 3.0
 +
| pcie lanes        = 16
 +
| pcie config        = 1x16
 +
| pcie config 2      = 2x8
 +
| pcie config 3      = 1x8+2x4
 
}}
 
}}
  
 
== Graphics ==
 
== Graphics ==
−
{{integrated graphic
+
{{integrated graphics
−
| gpu               = Intel HD Graphics 530
+
| gpu                 = HD Graphics 530
−
| device id         = 0x191B
+
| device id           = 0x191B
−
| displays           = 3
+
| designer            = Intel
−
| frequency         = 350 MHz
+
| execution units    = 24
−
| max frequency     = 900 MHz
+
| max displays       = 3
−
| max memory         = 64 GiB
+
| max memory          = 64 GiB
−
| output edp         = Yes
+
| frequency           = 350 MHz
−
| output dp         = Yes
+
| max frequency       = 900 MHz
−
| output hdmi       = Yes
+
 
−
| output vga         =  
+
| output crt          =
−
| output dvi         = Yes
+
| output sdvo         =  
 +
| output dsi          =
 +
| output edp         = Yes
 +
| output dp           = Yes
 +
| output hdmi         = Yes
 +
| output vga         =  
 +
| output dvi         = Yes
 +
 
 
| directx ver        = 12
 
| directx ver        = 12
 
| opengl ver        = 4.4
 
| opengl ver        = 4.4
Line 85: Line 130:
 
| max res vga freq  =  
 
| max res vga freq  =  
  
−
| intel quick sync   = Yes
+
| features            = Yes
−
| intel intru 3d     = Yes
+
| intel quick sync     = Yes
−
| intel insider     = Yes
+
| intel intru 3d       = Yes
−
| intel widi         = Yes
+
| intel insider       =  
−
| intel fdi         =  
+
| intel widi           =  
−
| intel clear video = Yes
+
| intel fdi           =  
 +
| intel clear video   = Yes
 +
| intel clear video hd = Yes
 
}}
 
}}
 +
{{skylake hardware accelerated video table|col=1}}
  
−
== Memory controller ==
+
== Features ==
−
{{integrated memory controller
+
{{x86 features
−
| type              = DDR3L-1600
+
|real=Yes
−
| type 2            = LPDDR3-1866
+
|protected=Yes
−
| type 3            = DDR4-2133
+
|smm=Yes
−
| controllers        = 1
+
|fpu=Yes
−
| channels          = 2
+
|x8616=Yes
−
| ecc support        = No
+
|x8632=Yes
−
| max bandwidth      = 34.1 GB/s
+
|x8664=Yes
−
| bandwidth schan    =  
+
|nx=Yes
−
| bandwidth dchan    =  
+
|mmx=Yes
−
| bandwidth tchan    =  
+
|emmx=Yes
−
| bandwidth qchan    =  
+
|sse=Yes
−
| max memory        = 64 GiB
+
|sse2=Yes
−
}}
+
|sse3=Yes
−
 
+
|ssse3=Yes
−
== Expansions ==
+
|sse41=Yes
−
{{mpu expansions
+
|sse42=Yes
−
| pcie revision      = 3.0
+
|sse4a=No
−
| pcie lanes        = 16
+
|avx=Yes
−
| pcie config        = 1x16
+
|avx2=Yes
−
| pcie config 1      = 2x8
 
−
| pcie config 2      = 1x8+2x4
 
−
| usb revision      =
 
−
| usb revision 2    =
 
−
| usb ports          =
 
−
| sata ports        =  
 
−
| integrated lan    =  
 
−
| uart              =  
 
−
| gp io              =
 
−
}}
 
  
−
== Features ==  
+
|abm=Yes
−
{{mpu features
+
|tbm=No
−
| em64t      = Yes
+
|bmi1=Yes
−
| nx          = Yes
+
|bmi2=Yes
−
| txt        =  
+
|fma3=Yes
−
| tsx        =  
+
|fma4=No
−
| vpro        =  
+
|aes=Yes
−
| ht          = Yes
+
|rdrand=Yes
−
| tbt1       =
+
|sha=No
−
| tbt2       =  
+
|xop=No
−
| bpt         =  
+
|adx=Yes
−
| vt-x        = Yes
+
|clmul=Yes
−
| vt-d        = Yes
+
|f16c=Yes
−
| ept        = Yes
+
|tbt1=No
−
| mmx        = Yes
+
|tbt2=No
−
| sse        = Yes
+
|tbmt3=No
−
| sse2        = Yes
+
|bpt=No
−
| sse3        = Yes
+
|eist=Yes
−
| ssse3      = Yes
+
|sst=No
−
| sse4        = Yes
+
|flex=Yes
−
| sse4.1      = Yes
+
|fastmem=No
−
| sse4.2      = Yes
+
|isrt=Yes
−
| aes        = Yes
+
|sba=No
−
| pclmul      = Yes
+
|mwt=Yes
−
| avx        = Yes
+
|sipp=No
−
| avx2        = Yes
+
|att=No
−
| bmi        = Yes
+
|ipt=Yes
−
| bmi1        = Yes
+
|tsx=No
−
| bmi2        = Yes
+
|txt=No
−
| f16c        = Yes
+
|ht=Yes
−
| fma3        = Yes
+
|vpro=No
−
| mpx        = Yes
+
|vtx=Yes
−
| sgx        = Yes
+
|vtd=Yes
−
| eist        = Yes
+
|ept=Yes
−
| secure key  = Yes
+
|mpx=Yes
−
| os guard    = Yes
+
|sgx=Yes
−
| intel at    =  
+
|securekey=Yes
 +
|osguard=Yes
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 
}}
 
}}

Latest revision as of 01:11, 16 January 2019

Edit Values
Core i3-6100H
skylake h (front).png
General Info
DesignerIntel
ManufacturerIntel
Model Numberi3-6100H
Part NumberCL8066202194634
S-SpecSR2FR
MarketMobile
IntroductionSeptember 1, 2015 (announced)
September 27, 2015 (launched)
End-of-lifeApril 19, 2019 (last order)
October 18, 2019 (last shipment)
Release Price$225
ShopAmazon
General Specs
FamilyCore i3
Seriesi3-6000
LockedYes
Frequency2,700 MHz
Bus typeDMI 3.0
Bus rate4 × 8 GT/s
Clock multiplier27
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureSkylake
Core NameSkylake H
Core Family6
Core Model94
Core SteppingR0
Process14 nm
TechnologyCMOS
Die98.57 mm²
10.3 mm × 9.57 mm
Word Size64 bit
Cores2
Threads4
Max Memory64 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Vcore0.55 V-1.52 V
TDP35 W
OP Temperature0 °C – 100 °C
Tjunction0 °C – 100 °C
Tstorage-25 °C – 125 °C
Packaging
PackageFCBGA-1440 (BGA)
Dimension42 mm x 28 mm x 1.49 mm
Pitch0.65 mm
Ball Count1440
Ball CompSAC405
InterconnectBGA-1440

Core i3-6100H is a 64-bit dual-core x86 low-end mobile microprocessor introduced by Intel in late 2015. The i3-6100H, which is based on the Skylake microarchitecture and is fabricated on a 14 nm process, has a base frequency of 2.7 GHz with a TDP of 35 W. This processor incorporates the HD Graphics 530 integrated graphics operating at 350 MHz with a turbo frequency of 900 MHz. This model supports 64 GiB of dual-channel DDR4-2133 memory.

Cache[edit]

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associativewrite-back
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  2x256 KiB4-way set associativewrite-back
L3$3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
  2x1.5 MiB write-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR3-1866, DDR3L-1600, DDR4-2133
Supports ECCNo
Max Mem64 GiB
Controllers1
Channels2
Max Bandwidth31.79 GiB/s
32,552.96 MiB/s
34.134 GB/s
34,134.253 MB/s
0.031 TiB/s
0.0341 TB/s
Bandwidth
Single 15.89 GiB/s
Double 31.79 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes16
Configs1x16, 2x8, 1x8+2x4


Graphics[edit]

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUHD Graphics 530
DesignerIntelDevice ID0x191B
Execution Units24Max Displays3
Max Memory64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
Frequency350 MHz
0.35 GHz
350,000 KHz
Burst Frequency900 MHz
0.9 GHz
900,000 KHz
OutputDP, eDP, HDMI, DVI
Max Resolution
HDMI4096x2304 @24 Hz
DP4096x2304 @60 Hz
eDP4096x2304 @60 Hz
Standards
DirectX12
OpenGL4.4
OpenCL2.0
DP1.2
eDP1.3
HDMI1.4a
Additional Features
Intel Quick Sync Video
Intel InTru 3D
Intel Clear Video
Intel Clear Video HD

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
EISTEnhanced SpeedStep Technology
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
MPXMemory Protection Extensions
SGXSoftware Guard Extensions
Secure KeySecure Key Technology
SMEPOS Guard Technology
Flex MemoryFlex Memory Access
ISRTSmart Response Technology
MWTMy WiFi Technology
IPTIdentity Protection Technology
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/core_i3/i3-6100h&oldid=86166"
Facts about "Core i3-6100H - Intel"
RDF feed
device id0x191B +
has featureintegrated gpu +
integrated gpuIntel HD Graphics 530 +
integrated gpu base frequency350 MHz (0.35 GHz, 350,000 KHz) +
integrated gpu max frequency900 MHz (0.9 GHz, 900,000 KHz) +
integrated gpu max memory65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB) +
l1d$ description8-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description8-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description4-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ descriptionshared +
l3$ size3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) +