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Difference between revisions of "intel/core i3/i3-6100u"
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{{intel title|Core i3-6100U}} | {{intel title|Core i3-6100U}} | ||
− | {{ | + | {{chip |
|name=Core i3-6100U | |name=Core i3-6100U | ||
− | + | |image=skylake u (front; standard).png | |
− | |image=skylake ( | ||
|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
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|s-spec=SR2EU | |s-spec=SR2EU | ||
|market=Mobile | |market=Mobile | ||
− | |first announced= | + | |first announced=September 1, 2015 |
− | |first launched= | + | |first launched=September 27, 2015 |
+ | |release price=$281 | ||
|family=Core i3 | |family=Core i3 | ||
|series=i3-6000 | |series=i3-6000 | ||
Line 44: | Line 44: | ||
|ctdp down=7.5 W | |ctdp down=7.5 W | ||
|ctdp down frequency=800 MHz | |ctdp down frequency=800 MHz | ||
− | |||
− | |||
|tjunc min=0 °C | |tjunc min=0 °C | ||
|tjunc max=100 °C | |tjunc max=100 °C | ||
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|package module 1={{packages/intel/fcbga-1356}} | |package module 1={{packages/intel/fcbga-1356}} | ||
}} | }} | ||
− | '''Core i3-6100U''' is a {{arch|64}} [[dual-core]] entry-level performance [[x86]] mobile microprocessor introduced by [[Intel]] in late [[2015]]. Fabricated on a [[14 nm process]] based on the {{intel|Skylake}} microarchitecture, this processor operates at 2.3 GHz. The i3-6100U has a TDP of 15 W with a configurable-down | + | '''Core i3-6100U''' is a {{arch|64}} [[dual-core]] entry-level performance [[x86]] mobile microprocessor introduced by [[Intel]] in late [[2015]]. Fabricated on a [[14 nm process]] based on the {{intel|Skylake}} microarchitecture, this processor operates at 2.3 GHz. The i3-6100U has a TDP of 15 W with a configurable TDP-down of 7.5 W. This chip incorporates the {{intel|HD Graphics 520}} GPU operating at 300 MHz with a burst frequency of 1 GHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory. |
== Cache == | == Cache == | ||
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|avx=Yes | |avx=Yes | ||
|avx2=Yes | |avx2=Yes | ||
− | + | ||
|abm=Yes | |abm=Yes | ||
|tbm=No | |tbm=No | ||
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|fma4=No | |fma4=No | ||
|aes=Yes | |aes=Yes | ||
− | |rdrand= | + | |rdrand=Yes |
|sha=No | |sha=No | ||
|xop=No | |xop=No | ||
− | |adx= | + | |adx=Yes |
− | |clmul= | + | |clmul=Yes |
− | |f16c= | + | |f16c=Yes |
|tbt1=No | |tbt1=No | ||
|tbt2=No | |tbt2=No | ||
Line 192: | Line 190: | ||
|sipp=No | |sipp=No | ||
|att=No | |att=No | ||
− | |ipt= | + | |ipt=Yes |
|tsx=No | |tsx=No | ||
|txt=No | |txt=No |
Latest revision as of 16:17, 13 December 2017
Edit Values | |||||||||||||
Core i3-6100U | |||||||||||||
General Info | |||||||||||||
Designer | Intel | ||||||||||||
Manufacturer | Intel | ||||||||||||
Model Number | i3-6100U | ||||||||||||
Part Number | FJ8066201931104 | ||||||||||||
S-Spec | SR2EU | ||||||||||||
Market | Mobile | ||||||||||||
Introduction | September 1, 2015 (announced) September 27, 2015 (launched) | ||||||||||||
Release Price | $281 | ||||||||||||
Shop | Amazon | ||||||||||||
General Specs | |||||||||||||
Family | Core i3 | ||||||||||||
Series | i3-6000 | ||||||||||||
Locked | Yes | ||||||||||||
Frequency | 2,300 MHz | ||||||||||||
Bus type | OPI | ||||||||||||
Bus rate | 4 GT/s | ||||||||||||
Clock multiplier | 23 | ||||||||||||
Microarchitecture | |||||||||||||
ISA | x86-64 (x86) | ||||||||||||
Microarchitecture | Skylake | ||||||||||||
Core Name | Skylake U | ||||||||||||
Core Family | 6 | ||||||||||||
Core Model | 78 | ||||||||||||
Core Stepping | D1 | ||||||||||||
Process | 14 nm | ||||||||||||
Transistors | 1,750,000,000 | ||||||||||||
Technology | CMOS | ||||||||||||
Die | 98.57 mm² 10.3 mm × 9.57 mm | ||||||||||||
MCP | Yes (2 dies) | ||||||||||||
Word Size | 64 bit | ||||||||||||
Cores | 2 | ||||||||||||
Threads | 4 | ||||||||||||
Max Memory | 32 GiB | ||||||||||||
Multiprocessing | |||||||||||||
Max SMP | 1-Way (Uniprocessor) | ||||||||||||
Electrical | |||||||||||||
Vcore | 0.55 V-1.52 V | ||||||||||||
TDP | 15 W | ||||||||||||
cTDP down | 7.5 W | ||||||||||||
cTDP down frequency | 800 MHz | ||||||||||||
Tjunction | 0 °C – 100 °C | ||||||||||||
Tstorage | -25 °C – 125 °C | ||||||||||||
Packaging | |||||||||||||
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Core i3-6100U is a 64-bit dual-core entry-level performance x86 mobile microprocessor introduced by Intel in late 2015. Fabricated on a 14 nm process based on the Skylake microarchitecture, this processor operates at 2.3 GHz. The i3-6100U has a TDP of 15 W with a configurable TDP-down of 7.5 W. This chip incorporates the HD Graphics 520 GPU operating at 300 MHz with a burst frequency of 1 GHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory.
Cache[edit]
- Main article: Skylake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Expansions[edit]
Expansion Options
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Graphics[edit]
Integrated Graphics Information
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[Edit] Skylake (Gen9) Hardware Accelerated Video Capabilities | |||||||
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Codec | Encode | Decode | |||||
Profiles | Levels | Max Resolution | Profiles | Levels | Max Resolution | ||
MPEG-2 (H.262) | Main | High | 1080p (FHD) | Main | Main, High | 1080p (FHD) | |
MPEG-4 AVC (H.264) | High, Main | 5.1 | 2160p (4K) | Main, High, SHP, MHP | 5.1 | 2160p (4K) | |
JPEG/MJPEG | Baseline | - | 16k x 16k | Baseline | Unified | 16k x 16k | |
HEVC (H.265) | Main | 5.1 | 2160p (4K) | Main, Main 10 | 5.1 | 2160p (4K) | |
VC-1 | ✘ | Advanced, Main, Simple | 3, High | 3840x3840 | |||
VP8 | Unified | Unified | - | 0 | Unified | 1080p | |
VP9 | ✘ | 0 | Unified | 2160p (4K) |
Features[edit]
[Edit/Modify Supported Features]
Facts about "Core i3-6100U - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Core i3-6100U - Intel#io + |
device id | 0x1916 + |
has ecc memory support | false + |
integrated gpu | HD Graphics 520 + |
integrated gpu base frequency | 300 MHz (0.3 GHz, 300,000 KHz) + |
integrated gpu designer | Intel + |
integrated gpu execution units | 24 + |
integrated gpu max frequency | 1,000 MHz (1 GHz, 1,000,000 KHz) + |
integrated gpu max memory | 32,768 MiB (33,554,432 KiB, 34,359,738,368 B, 32 GiB) + |
l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
l3$ size | 3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) + |
max memory bandwidth | 31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) + |
max memory channels | 2 + |
max pcie lanes | 12 + |
supported memory type | DDR4-2133 +, LPDDR3-1866 + and DDR3L-1600 + |