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'''VY86C810''' is a {{arch|32}} [[ARM]] microprocessor designed by [[arm holdings|ARM]] and introduce by [[vti|VTI]] in [[1996]]. This processor is based on the {{armh|ARM8|l=arch}} microarchitecture ({{armh|ARM810|l=core}} core) and is manufactured on [[VLSI Technology|VLSI]]'s [[0.5 µm process]] and operating at 50 MHz.
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== Cache ==
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{{main|arm_holdings/microarchitectures/arm8#Memory_Hierarchy|l1=ARM8 § Cache}}
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{{cache size
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|l1 cache=8 KiB
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|l1 break=1x8 KiB
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|l1 desc=64-way set associative
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|l1 policy=write-through
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}}
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== Documents ==
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* [[:File:vlsi arm810-710.pdf|VY86C710A/VY86C710A2/VY86C810 Product Brief]]

Latest revision as of 16:32, 13 December 2017

Edit Values
VY86C810
General Info
DesignerARM Holdings
ManufacturerVLSI Technology
Model NumberVY86C810
Part NumberVY86C810
MarketEmbedded, Desktop
IntroductionAugust 26, 1996 (announced)
November, 1996 (launched)
General Specs
FamilyVL86Cx
Frequency50 MHz
Microarchitecture
ISAARMv4 (ARM)
MicroarchitectureARM8
Core NameARM810
Process0.5 µm
TechnologyCMOS
Die53.5 mm²
Word Size32 bit
Cores1
Threads1
Max Memory4 GiB
Max Address Mem0xFFFFFFFF
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Power dissipation500 mW
Vcore3.3 V ± 10 %
Tstorage-65 °C – -150 °C
Tambient-10 °C – 70 °C
Packaging
PackageTQFP-144 (TQFP)
Dimension20 mm x 20 mm x 1.6 mm
Pitch0.5 mm
Pin Count144

VY86C810 is a 32-bit ARM microprocessor designed by ARM and introduce by VTI in 1996. This processor is based on the ARM8 microarchitecture (ARM810 core) and is manufactured on VLSI's 0.5 µm process and operating at 50 MHz.

Cache[edit]

Main article: ARM8 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$8 KiB
8,192 B
0.00781 MiB
  1x8 KiB64-way set associativewrite-through

Documents[edit]

Facts about "VY86C810 - VTI"
l1$ description64-way set associative +
l1$ size8 KiB (8,192 B, 0.00781 MiB) +