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Difference between revisions of "vti/vl86cx/vy86c610"
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{{vti title|VY86C610}} | {{vti title|VY86C610}} | ||
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|name=VY86C610 | |name=VY86C610 | ||
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|core name=ARM610 | |core name=ARM610 | ||
|process=0.8 µm | |process=0.8 µm | ||
| − | |transistors= | + | |transistors=358,931 |
|technology=CMOS | |technology=CMOS | ||
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|max memory=4 GiB | |max memory=4 GiB | ||
|max memory addr=0xFFFFFFFF | |max memory addr=0xFFFFFFFF | ||
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|v core tolerance=5 % | |v core tolerance=5 % | ||
|tstorage min=-65 °C | |tstorage min=-65 °C | ||
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|package module 1={{packages/vti/tqfp-144}} | |package module 1={{packages/vti/tqfp-144}} | ||
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| − | '''VY86C610''' is a {{arch|32}} [[ARM]] microprocessor designed by [[arm holdings|ARM]] and introduce by [[vti|VTI]] in [[1993]]. This processor is based on the {{armh|ARM6|l=arch}} microarchitecture ({{armh|ARM610|l=core}} core) which was manufactured on [[VLSI Technology|VLSI]]'s [[0.8 µm process]] and operated at 20 MHz. | + | '''VY86C610''' is a {{arch|32}} [[ARM]] microprocessor designed by [[arm holdings|ARM]] and introduce by [[vti|VTI]] in [[1993]]. This processor is based on the {{armh|ARM6|l=arch}} microarchitecture ({{armh|ARM610|l=core}} core) which was manufactured on [[VLSI Technology|VLSI]]'s [[0.8 µm process]] and operated at 20 MHz and 25 MHz. |
This processor, unlike its {{armh|ARM60|l=core}} variant which only incorporate the bare bone core, includes a cache, write buffer, and a [[memory management unit]]. | This processor, unlike its {{armh|ARM60|l=core}} variant which only incorporate the bare bone core, includes a cache, write buffer, and a [[memory management unit]]. | ||
Latest revision as of 15:32, 13 December 2017
| Edit Values | |||||||||
| VY86C610 | |||||||||
| General Info | |||||||||
| Designer | ARM Holdings | ||||||||
| Manufacturer | VLSI Technology | ||||||||
| Model Number | VY86C610 | ||||||||
| Part Number | VY86C61020BC, VY86C610-25 | ||||||||
| Market | Embedded, Desktop | ||||||||
| Introduction | 1993 (launched) | ||||||||
| Release Price | $25 | ||||||||
| General Specs | |||||||||
| Family | VL86Cx | ||||||||
| Frequency | 20 MHz, 25 MHz | ||||||||
| Microarchitecture | |||||||||
| ISA | ARMv3 (ARM) | ||||||||
| Microarchitecture | ARM6 | ||||||||
| Chipset | MEMC, VIDC, IOC | ||||||||
| Core Name | ARM610 | ||||||||
| Process | 0.8 µm | ||||||||
| Transistors | 358,931 | ||||||||
| Technology | CMOS | ||||||||
| Word Size | 32 bit | ||||||||
| Cores | 1 | ||||||||
| Threads | 1 | ||||||||
| Max Memory | 4 GiB | ||||||||
| Max Address Mem | 0xFFFFFFFF | ||||||||
| Multiprocessing | |||||||||
| Max SMP | 1-Way (Uniprocessor) | ||||||||
| Electrical | |||||||||
| Vcore | 5 V ± 5 % | ||||||||
| Tstorage | -65 °C – -150 °C | ||||||||
| Tambient | -10 °C – 70 °C | ||||||||
| Packaging | |||||||||
| |||||||||
VY86C610 is a 32-bit ARM microprocessor designed by ARM and introduce by VTI in 1993. This processor is based on the ARM6 microarchitecture (ARM610 core) which was manufactured on VLSI's 0.8 µm process and operated at 20 MHz and 25 MHz.
This processor, unlike its ARM60 variant which only incorporate the bare bone core, includes a cache, write buffer, and a memory management unit.
Cache[edit]
- Main article: ARM6 § Cache
 |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Datasheet[edit]
- VY86C610 Datasheet, September 1993
Facts about "VY86C610 - VTI"
| l1$ description | 64-way set associative + |
| l1$ size | 4 KiB (4,096 B, 0.00391 MiB) + |