Difference between revisions of "cavium/octeon plus/cn5840-600bg1521-exp"

	Edit Values
	Cavium CN5840-600 EXP
	General Info
Designer	Cavium
Manufacturer	TSMC
Model Number	CN5840-600 EXP
Part Number	CN5840-600BG1521-EXP
Market	Network
Introduction	October 9, 2006 (announced); February, 2007 (launched)
	General Specs
Family	OCTEON Plus
Series	CN58xx
Frequency	600 MHz
	Microarchitecture
ISA	MIPS64 (MIPS)
Microarchitecture	cnMIPS
Process	90 nm
Technology	CMOS
Word Size	64 bit
Cores	8
Threads	8
	Multiprocessing
Max SMP	1-Way (Uniprocessor)
	Packaging
Package	FCBGA-1521 (BGA)
Ball Count	1521
Interconnect	BGA-1521

Latest revision as of 15:12, 13 December 2017

CN5840-600 EXP is a 64-bit octa-core MIPS network microprocessor designed by Cavium and introduced in 2007. This processor, which incorporates eight cnMIPS cores, operates at 600 MHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of various software such as RegEx, compression/decompression, and TCP acceleration.

Cache[edit]

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

384 KiB

393,216 B
0.375 MiB

L1I$	256 KiB 262,144 B 0.25 MiB	8x32 KiB	64-way set associative
L1D$	128 KiB 131,072 B 0.125 MiB	8x16 KiB	64-way set associative

L2$

2 MiB

2,048 KiB
2,097,152 B
0.00195 GiB

		1x2 MiB	8-way set associative

Memory controller[edit]

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	DDR2-800
Supports ECC	Yes
Controllers	1
Channels	1
Width	128 bit
Max Bandwidth	11.92 GiB/s 12,206.08 MiB/s 12.799 GB/s 12,799.003 MB/s 0.0116 TiB/s 0.0128 TB/s
Bandwidth	Single 11.92 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

Expansion Options

PCI-X

Width	64 bit
Clock	133.33 MHz
Rate	1,017.25 MiB/s
Features	host or slave

UART

Ports	2

GP I/O	Yes

Networking[edit]

[Edit/Modify Network Info]

Networking

MII

RGMII	Yes (Ports: 8)

SPI

SPI-4.2	Yes (Ports: 2)

Hardware Accelerators[edit]

[Edit/Modify Accelerators Info]

Hardware Accelerators

RegEx

RegEx	Yes
Features	32 Engines

Networking

TCP	Yes
QoS	Yes

Compression

Compression	Yes
Decompression	Yes

Block diagram[edit]

Datasheet[edit]

OCTEON CN58XX Processors Product Brief

@@ Line 1: / Line 1: @@
 {{cavium title|CN5840-600 EXP}}
-{{mpu
+{{chip
 | name                = Cavium CN5840-600 EXP
 | no image            =

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	CN5840-600 EXP - Cavium#package +
base frequency	600 MHz (0.6 GHz, 600,000 kHz) +
core count	8 +
designer	Cavium +
family	OCTEON Plus +
first announced	October 9, 2006 +
first launched	February 2007 +
full page name	cavium/octeon plus/cn5840-600bg1521-exp +
has ecc memory support	true +
has hardware accelerators for data compression	true +
has hardware accelerators for data decompression	true +
has hardware accelerators for network quality of service processing	true +
has hardware accelerators for regular expression	true +
has hardware accelerators for tcp packet processing	true +
instance of	microprocessor +
isa	MIPS64 +
isa family	MIPS +
l1$ size	384 KiB (393,216 B, 0.375 MiB) +
l1d$ description	64-way set associative +
l1d$ size	128 KiB (131,072 B, 0.125 MiB) +
l1i$ description	64-way set associative +
l1i$ size	256 KiB (262,144 B, 0.25 MiB) +
l2$ description	8-way set associative +
l2$ size	2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
ldate	February 2007 +
main image	+
manufacturer	TSMC +
market segment	Network +
max cpu count	1 +
max memory bandwidth	11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels	1 +
microarchitecture	cnMIPS +
model number	CN5840-600 EXP +
name	Cavium CN5840-600 EXP +
package	FCBGA-1521 +
part number	CN5840-600BG1521-EXP +
process	90 nm (0.09 μm, 9.0e-5 mm) +
series	CN58xx +
smp max ways	1 +
supported memory type	DDR2-800 +
technology	CMOS +
thread count	8 +
word size	64 bit (8 octets, 16 nibbles) +

WikiChip

The Fuse Coverage

Social Media

Companies

Microarchitectures

Technology Nodes

Intel

AMD

ARM

Cavium

Samsung

Intel

AMD

Ampere

Apple

Cavium

HiSilicon

MediaTek

NXP

Qualcomm

Renesas