Difference between revisions of "cavium/octeon/cn3850-400bg1521-exp"

	Edit Values
	Cavium CN3850-400 EXP
	General Info
Designer	Cavium
Manufacturer	TSMC
Model Number	CN3850-400 EXP
Part Number	CN3850-400BG1521-EXP
Market	Networking
Introduction	August 22, 2005 (announced); August 22, 2005 (launched)
	General Specs
Family	OCTEON
Series	CN3800
Frequency	400 MHz
	Microarchitecture
ISA	MIPS64 (MIPS)
Microarchitecture	cnMIPS
Core Name	cnMIPS
Process	130 nm
Technology	CMOS
Word Size	64 bit
Cores	12
Threads	12
Max Memory	16 GiB
	Multiprocessing
Max SMP	1-Way (Uniprocessor)
	Packaging
Package	FCBGA-1521 (BGA)
Ball Count	1521
Interconnect	BGA-1521

Latest revision as of 16:11, 13 December 2017

The CN3850-400 EXP is a 64-bit dodeca-core MIPS communication microprocessor designed by Cavium and introduced in 2005. This processor, which incorporates twelve cnMIPS cores, operates at 400 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.

Cache[edit]

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

480 KiB

491,520 B
0.469 MiB

L1I$	384 KiB 393,216 B 0.375 MiB	12x32 KiB	64-way set associative
L1D$	96 KiB 98,304 B 0.0938 MiB	12x8 KiB	64-way set associative	Write-through

L2$

1 MiB

1,024 KiB
1,048,576 B
9.765625e-4 GiB

		1x1 MiB	8-way set associative

Memory controller[edit]

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	DDR2-800
Supports ECC	Yes
Max Mem	16 GiB
Controllers	1
Channels	1
Width	128 bit
Max Bandwidth	11.92 GiB/s 12,206.08 MiB/s 12.799 GB/s 12,799.003 MB/s 0.0116 TiB/s 0.0128 TB/s
Bandwidth	Single 11.92 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

Expansion Options

PCI-X

Width	64 bit
Clock	133.33 MHz
Rate	1,017.25 MiB/s
Features	host or slave

UART

Ports	2

GP I/O	Yes

Networking[edit]

[Edit/Modify Network Info]

Networking

MII

RGMII	Yes (Ports: 8)

SPI

SPI-4.2	Yes (Ports: 2)

Hardware Accelerators[edit]

[Edit/Modify Accelerators Info]

Hardware Accelerators

RegEx

RegEx	Yes
Features	16 Engines

Networking

TCP	Yes
QoS	Yes

Compression

Compression	Yes
Decompression	Yes

Block diagram[edit]

Datasheet[edit]

OCTEON CN38XX/CN36XX 4 to 16-Core Product Brief

@@ Line 1: / Line 1: @@
 {{cavium title|CN3850-400 EXP}}
-{{mpu
+{{chip
 | name                = Cavium CN3850-400 EXP
 | no image            =

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	CN3850-400 EXP - Cavium#package +
base frequency	400 MHz (0.4 GHz, 400,000 kHz) +
core count	12 +
core name	cnMIPS +
designer	Cavium +
family	OCTEON +
first announced	August 22, 2005 +
first launched	August 22, 2005 +
full page name	cavium/octeon/cn3850-400bg1521-exp +
has ecc memory support	true +
has hardware accelerators for data compression	true +
has hardware accelerators for data decompression	true +
has hardware accelerators for network quality of service processing	true +
has hardware accelerators for regular expression	true +
has hardware accelerators for tcp packet processing	true +
instance of	microprocessor +
isa	MIPS64 +
isa family	MIPS +
l1$ size	480 KiB (491,520 B, 0.469 MiB) +
l1d$ description	64-way set associative +
l1d$ size	96 KiB (98,304 B, 0.0938 MiB) +
l1i$ description	64-way set associative +
l1i$ size	384 KiB (393,216 B, 0.375 MiB) +
l2$ description	8-way set associative +
l2$ size	1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
ldate	August 22, 2005 +
main image	+
manufacturer	TSMC +
market segment	Networking +
max cpu count	1 +
max memory	16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB, 0.0156 TiB) +
max memory bandwidth	11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels	1 +
microarchitecture	cnMIPS +
model number	CN3850-400 EXP +
name	Cavium CN3850-400 EXP +
package	FCBGA-1521 +
part number	CN3850-400BG1521-EXP +
process	130 nm (0.13 μm, 1.3e-4 mm) +
series	CN3800 +
smp max ways	1 +
supported memory type	DDR2-800 +
technology	CMOS +
thread count	12 +
word size	64 bit (8 octets, 16 nibbles) +

WikiChip

The Fuse Coverage

Social Media

Companies

Microarchitectures

Technology Nodes

Intel

AMD

ARM

Cavium

Samsung

Intel

AMD

Ampere

Apple

Cavium

HiSilicon

MediaTek

NXP

Qualcomm

Renesas