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Difference between revisions of "amd/ryzen 5/pro 1600"
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{{amd title|Ryzen 5 PRO 1600}} | {{amd title|Ryzen 5 PRO 1600}} | ||
− | {{ | + | {{chip |
+ | |future=Yes | ||
|name=Ryzen 5 PRO 1600 | |name=Ryzen 5 PRO 1600 | ||
|no image=Yes | |no image=Yes | ||
Line 6: | Line 7: | ||
|manufacturer=GlobalFoundries | |manufacturer=GlobalFoundries | ||
|model number=PRO 1600 | |model number=PRO 1600 | ||
+ | |part number=YD160BBBM6IAE | ||
|market=Desktop | |market=Desktop | ||
|first announced=June 29, 2017 | |first announced=June 29, 2017 | ||
Line 13: | Line 15: | ||
|frequency=3,200 MHz | |frequency=3,200 MHz | ||
|turbo frequency1=3,600 MHz | |turbo frequency1=3,600 MHz | ||
+ | |turbo frequency2=3,600 MHz | ||
+ | |turbo frequency3=3,300 MHz | ||
+ | |turbo frequency4=3,300 MHz | ||
+ | |turbo frequency5=3,300 MHz | ||
+ | |turbo frequency6=3,300 MHz | ||
|bus links=4 | |bus links=4 | ||
|bus rate=8 GT/s | |bus rate=8 GT/s | ||
Line 23: | Line 30: | ||
|core family=23 | |core family=23 | ||
|core model=1 | |core model=1 | ||
− | |core stepping= | + | |core stepping=B1 |
|process=14 nm | |process=14 nm | ||
|transistors=4,800,000,000 | |transistors=4,800,000,000 | ||
|technology=CMOS | |technology=CMOS | ||
− | |die area= | + | |die area=213 mm² |
− | |||
− | |||
|word size=64 bit | |word size=64 bit | ||
|core count=6 | |core count=6 | ||
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|max memory=64 GiB | |max memory=64 GiB | ||
|tdp=65 W | |tdp=65 W | ||
− | |package | + | |package name 1=amd,socket am4 |
}} | }} | ||
− | '''Ryzen 5 PRO 1600''' is a {{arch|64}} [[hexa-core]] mid-range performance [[x86]] workstation microprocessor introduced by [[AMD]] in mid-[[2017]]. This processor is based on AMD's {{amd|Zen|Zen microarchitecture|l=arch}} and is fabricated on a [[14 nm process]]. The PRO 1600 operates at a base frequency of 3.2 GHz with a [[TDP]] of 65 W and a {{amd|Precision Boost|Boost}} frequency of 3.6 GHz. This MPU supports up to 64 GiB of dual-channel DDR4-2666 ECC memory. | + | '''Ryzen 5 PRO 1600''' is a {{arch|64}} [[hexa-core]] mid-range performance [[x86]] workstation microprocessor introduced by [[AMD]] in mid-[[2017]]. This processor is based on AMD's {{amd|Zen|Zen microarchitecture|l=arch}} and is fabricated on a [[14 nm process]]. The PRO 1600 operates at a base frequency of 3.2 GHz with a [[TDP]] of 65 W and a {{amd|Precision Boost|Boost}} frequency of up to 3.6 GHz. This MPU supports up to 64 GiB of dual-channel DDR4-2666 ECC memory. |
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{{main|amd/microarchitectures/zen#Memory_Hierarchy|l1=Zen § Cache}} | {{main|amd/microarchitectures/zen#Memory_Hierarchy|l1=Zen § Cache}} | ||
{{cache size | {{cache size | ||
− | |l1 cache= | + | |l1 cache=576 KiB |
− | |l1i cache= | + | |l1i cache=384 KiB |
− | |l1i break= | + | |l1i break=6x64 KiB |
|l1i desc=4-way set associative | |l1i desc=4-way set associative | ||
− | |l1d cache= | + | |l1d cache=192 KiB |
− | |l1d break= | + | |l1d break=6x32 KiB |
|l1d desc=8-way set associative | |l1d desc=8-way set associative | ||
|l1d policy=write-back | |l1d policy=write-back | ||
− | |l2 cache= | + | |l2 cache=3 MiB |
− | |l2 break= | + | |l2 break=6x512 KiB |
|l2 desc=8-way set associative | |l2 desc=8-way set associative | ||
|l2 policy=write-back | |l2 policy=write-back | ||
Line 122: | Line 127: | ||
|avx=Yes | |avx=Yes | ||
|avx2=Yes | |avx2=Yes | ||
− | | | + | |avx512f=No |
+ | |avx512cd=No | ||
+ | |avx512er=No | ||
+ | |avx512pf=No | ||
+ | |avx512bw=No | ||
+ | |avx512dq=No | ||
+ | |avx512vl=No | ||
+ | |avx512ifma=No | ||
+ | |avx512vbmi=No | ||
+ | |avx5124fmaps=No | ||
+ | |avx5124vnniw=No | ||
+ | |avx512vpopcntdq=No | ||
|abm=Yes | |abm=Yes | ||
|tbm=No | |tbm=No | ||
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|flex=No | |flex=No | ||
|fastmem=No | |fastmem=No | ||
+ | |ivmd=No | ||
+ | |intelnodecontroller=No | ||
+ | |intelnode=No | ||
+ | |kpt=No | ||
+ | |ptt=No | ||
+ | |intelrunsure=No | ||
+ | |mbe=No | ||
|isrt=No | |isrt=No | ||
|sba=No | |sba=No | ||
Line 161: | Line 184: | ||
|securekey=No | |securekey=No | ||
|osguard=No | |osguard=No | ||
+ | |intqat=No | ||
|3dnow=No | |3dnow=No | ||
|e3dnow=No | |e3dnow=No | ||
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|amdvi=Yes | |amdvi=Yes | ||
|amdv=Yes | |amdv=Yes | ||
+ | |amdsme=No | ||
+ | |amdtsme=Yes | ||
+ | |amdsev=No | ||
|rvi=No | |rvi=No | ||
|smt=Yes | |smt=Yes | ||
|sensemi=Yes | |sensemi=Yes | ||
|xfr=No | |xfr=No | ||
+ | |mxfr=No | ||
+ | |amdpb=Yes | ||
+ | |amdpb2=No | ||
}} | }} | ||
+ | |||
+ | * This model has partial {{amd|XFR}} support, allowing for an additional +[[amd xfr headroom::100]] MHz boost frequency. |
Latest revision as of 22:55, 25 March 2023
Edit Values | |
Ryzen 5 PRO 1600 | |
General Info | |
Designer | AMD |
Manufacturer | GlobalFoundries |
Model Number | PRO 1600 |
Part Number | YD160BBBM6IAE |
Market | Desktop |
Introduction | June 29, 2017 (announced) |
Shop | Amazon |
General Specs | |
Family | Ryzen 5 |
Series | Ryzen PRO |
Locked | No |
Frequency | 3,200 MHz |
Turbo Frequency | 3,600 MHz (1 core), 3,600 MHz (2 cores), 3,300 MHz (3 cores), 3,300 MHz (4 cores), 3,300 MHz (5 cores), 3,300 MHz (6 cores) |
Bus rate | 4 × 8 GT/s |
Clock multiplier | 32 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Zen |
Chipset | Promontory |
Core Name | Summit Ridge |
Core Family | 23 |
Core Model | 1 |
Core Stepping | B1 |
Process | 14 nm |
Transistors | 4,800,000,000 |
Technology | CMOS |
Die | 213 mm² |
Word Size | 64 bit |
Cores | 6 |
Threads | 12 |
Max Memory | 64 GiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
TDP | 65 W |
Packaging | |
Package | OPGA-1331 |
Package Type | Organic Micro Pin Grid Array |
Dimension | 40 mm × 40 mm |
Pitch | 1 mm |
Contacts | 1331 |
Socket | Socket AM4 |
Ryzen 5 PRO 1600 is a 64-bit hexa-core mid-range performance x86 workstation microprocessor introduced by AMD in mid-2017. This processor is based on AMD's Zen microarchitecture and is fabricated on a 14 nm process. The PRO 1600 operates at a base frequency of 3.2 GHz with a TDP of 65 W and a Boost frequency of up to 3.6 GHz. This MPU supports up to 64 GiB of dual-channel DDR4-2666 ECC memory.
Cache[edit]
- Main article: Zen § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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[Edit] Memory Configurations | |||
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Dual Channel | Single Rank | 2 DIMMs | DDR4-2666 |
4 DIMMs | DDR4-2133 | ||
Double Rank | 2 DIMMs | DDR4-2400 | |
4 DIMMs | DDR4-1866 |
Expansions[edit]
This processors has 20 PCIe lanes: 16 for a DGP and 4 for storage (NVMe or 2 ports SATA Express).
Expansion Options
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- eMMC, LPC, SMBus, SPI/eSPI
Audio[edit]
Support Azalia High Definition Audio
Graphics[edit]
This processor has no integrated graphics.
Features[edit]
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
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- This model has partial XFR support, allowing for an additional +100100 MHzMHz boost frequency.
0.1 GHz
100,000 kHz
Facts about "Ryzen 5 PRO 1600 - AMD"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Ryzen 5 PRO 1600 - AMD#io + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has amd amd-v technology | true + |
has amd amd-vi technology | true + |
has amd sensemi technology | true + |
has ecc memory support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension + and SenseMI Technology + |
has simultaneous multithreading | true + |
has x86 advanced encryption standard instruction set extension | true + |
l1$ size | 576 KiB (589,824 B, 0.563 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 192 KiB (196,608 B, 0.188 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) + |
max memory bandwidth | 39.74 GiB/s (40,693.76 MiB/s, 42.671 GB/s, 42,670.5 MB/s, 0.0388 TiB/s, 0.0427 TB/s) + |
max memory channels | 2 + |
max pcie lanes | 20 + |
supported memory type | DDR4-2666 + |