Semiconductor & Computer Engineering
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Difference between revisions of "amd/duron/dhd1800dlv1c"
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{{amd title|Duron 1800 (Applebred)}} | {{amd title|Duron 1800 (Applebred)}} | ||
| − | {{ | + | {{chip |
| name = Duron 1800 | | name = Duron 1800 | ||
| no image = Yes | | no image = Yes | ||
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| model number = Duron 1800 | | model number = Duron 1800 | ||
| part number = DHD1800DLV1C | | part number = DHD1800DLV1C | ||
| − | |||
| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
| + | | part number 4 = | ||
| market = Desktop | | market = Desktop | ||
| first announced = August 15, 2003 | | first announced = August 15, 2003 | ||
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== Features == | == Features == | ||
| − | {{ | + | {{x86 features |
| em64t = | | em64t = | ||
| nx = | | nx = | ||
Latest revision as of 15:07, 13 December 2017
| Edit Values | |
| Duron 1800 | |
| General Info | |
| Designer | AMD |
| Manufacturer | AMD |
| Model Number | Duron 1800 |
| Part Number | DHD1800DLV1C |
| Market | Desktop |
| Introduction | August 15, 2003 (announced) August 15, 2003 (launched) |
| Shop | Amazon |
| General Specs | |
| Family | Duron |
| Series | Duron Desktop |
| Locked | Yes |
| Frequency | 1800 MHz |
| Bus type | FSB |
| Bus speed | 133.33 MHz |
| Bus rate | 266.66 MT/s |
| Clock multiplier | 13.5 |
| CPUID | 680 |
| Microarchitecture | |
| Microarchitecture | K7 |
| Core Name | Applebred |
| Core Family | 6 |
| Core Model | 8 |
| Core Stepping | 0, 1, 2 |
| Process | 130 nm |
| Transistors | 37,200,000 |
| Technology | CMOS |
| Die | 80.89 mm² |
| Word Size | 32 bit |
| Cores | 1 |
| Threads | 1 |
| Max Memory | 4 GiB |
| Multiprocessing | |
| Max SMP | 1-Way (Uniprocessor) |
| Electrical | |
| Vcore | 1.5 V ± 0.1 V |
| TDP | 57 W |
| Tcase | 0 °C – 85 °C |
| Tstorage | -40 °C – 100 °C |
The Duron 1800 based on the Applebred core was a 32-bit x86 microprocessor developed by AMD and introduced in mid-2003. This model was part of the third generation of the Duron family. Designed based on AMD's K7 and manufactured using their newer 130 nm process, this MPU operated at 1800 MHz with a bus capable of 266 MT/s with a max TDP of 57 W and a typical TDP of 53 W.
Cache[edit]
- Main article: K7 § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 64 KiB 65,536 B 0.0625 MiB |
1x64 KiB 2-way set associative |
| L1D$ | 64 KiB 65,536 B 0.0625 MiB |
1x64 KiB 2-way set associative |
| L2$ | 64 KiB 0.0625 MiB 65,536 B 6.103516e-5 GiB |
1x64 KiB 16-way set associative |
Graphics[edit]
This SoC has no integrated graphics processing unit.
Features[edit]
[Edit/Modify Supported Features]
 |
Supported x86 Extensions & Processor Features
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- Halt State
- Sleep State
Documents[edit]
DataSheet[edit]
- AMD Duron Processor Model 8 Data Sheet; Publication # 25848; Rev: B; Issue Date: August 2003.
See also[edit]
Facts about "Duron 1800 (Applebred) - AMD"
| has feature | Halt State + and Sleep State + |
| l1d$ description | 2-way set associative + |
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l1i$ description | 2-way set associative + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l2$ description | 16-way set associative + |
| l2$ size | 0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) + |