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Difference between revisions of "intel/core m/m5-6y54"
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{{intel title|Core M5-6Y54}}
+
{{intel title|Core m5-6Y54}}
−
{{mpu
+
{{chip
−
| name               = Core M5-6Y54
+
|name=Core m5-6Y54
−
| no image           =
+
|image=skylake y (front).png
−
| image              = skylake y (front).png
+
|image size=250px
−
| image size         = 250px
+
|designer=Intel
−
| caption            =
+
|manufacturer=Intel
−
| designer           = Intel
+
|model number=m5-6Y54
−
| manufacturer       = Intel
+
|part number=HE8066201930524
−
| model number       = M5-6Y54
+
|s-spec=SR2EM
−
| part number         = HE8066201930524
+
|market=Mobile
−
| market             = Mobile
+
|first announced=September 1, 2015
−
| first announced     =  
+
|first launched=September 27, 2015
−
| first launched     = September 1, 2015
+
|release price=$281
−
| last order          =
+
|family=Core m5
−
| last shipment      =
+
|series=m-6Y
−
| release price       = $281
+
|locked=Yes
−
 
+
|frequency=1100 MHz
−
| family             = Core M5
+
|turbo frequency1=2,700 MHz
−
| series             = 6000
+
|turbo frequency2=2,400 MHz
−
| locked             = Yes
+
|turbo frequency=Yes
−
| frequency           = 1100 MHz
+
|bus type=DMI 3.0
−
| turbo frequency    = Yes
+
|clock multiplier=11
−
| turbo frequency1    = 2700 MHz
+
|isa=x86-64
−
| turbo frequency2    =  
+
|isa family=x86
−
| bus type           = DMI 3.0
+
|microarch=Skylake
−
| bus speed          =
+
|platform=Skylake
−
| bus rate            =
+
|core name=Skylake Y
−
| clock multiplier   = 11
+
|core family=6
−
| s-spec              = SR2EM
+
|core model=78
−
| s-spec es          =
+
|core stepping=D1
−
| s-spec qs          =
+
|process=14 nm
−
| cpuid              =
+
|transistors=1,750,000,000
−
 
+
|technology=CMOS
−
| isa family         = x86
+
|die area=98.57 mm²
−
| isa                = x86-64
+
|die length=10.3 mm
−
| microarch           = Skylake
+
|die width=9.57 mm
−
| platform           = Skylake
+
|mcp=Yes
−
| chipset            =
+
|die count=2
−
| core name           = Skylake Y
+
|word size=64 bit
−
| core family         =  
+
|core count=2
−
| core model         =  
+
|thread count=4
−
| core stepping       = D1
+
|max cpus=1
−
| process             = 14 nm
+
|max memory=16 GiB
−
| transistors         = 1,750,000,000
+
|sdp=3 W
−
| technology         = CMOS
+
|tdp=4.5 W
−
| die area           = 98.57 mm²
+
|ctdp down=3.5 W
−
| die width           = 9.57 mm
+
|ctdp down frequency=600 MHz
−
| die length          = 10.3 mm
+
|ctdp up=7 W
−
| word size           = 64 bit
+
|ctdp up frequency=1500 MHz
−
| core count         = 2
+
|tjunc min=5 °C
−
| thread count       = 4
+
|tjunc max=100 °C
−
| max cpus           = 1
+
|package name 1=intel,fcbga_1515
−
| max memory         = 16 GiB
 
−
 
 
−
 
 
−
| v core              =
 
−
| v core tolerance    =
 
−
| sdp                 = 3 W
 
−
| tdp                 = 4.5 W
 
−
| ctdp down           = 3.5 W
 
−
| ctdp down frequency = 600 MHz
 
−
| ctdp up             = 7 W
 
−
| ctdp up frequency   = 1500 MHz
 
−
| tjunc min           = 5 °C
 
−
| tjunc max           = 100 °C
 
−
 
 
−
| package module 1 = {{packages/intel/fcbga-1515}}
 
 
}}
 
}}
 
'''Core M5-6Y54''' is an ultra-low power {{arch|64}} [[dual-core]] [[x86]] microprocessor introduced by [[Intel]] in late 2015. This MPU operates at 1.1 GHz with a max turbo frequency of 2.7 GHz. This chip, which is manufactured on a [[14 nm process]], is based on the {{intel|Skylake}} microarchitecture. The Core M5-6Y54 incorporates Intel's {{intel|HD Graphics 515}} Gen9 GPU clocked at 300 MHz with turbo frequency of 900 MHz.
 
'''Core M5-6Y54''' is an ultra-low power {{arch|64}} [[dual-core]] [[x86]] microprocessor introduced by [[Intel]] in late 2015. This MPU operates at 1.1 GHz with a max turbo frequency of 2.7 GHz. This chip, which is manufactured on a [[14 nm process]], is based on the {{intel|Skylake}} microarchitecture. The Core M5-6Y54 incorporates Intel's {{intel|HD Graphics 515}} Gen9 GPU clocked at 300 MHz with turbo frequency of 900 MHz.
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== Memory controller ==
 
== Memory controller ==
 
{{memory controller
 
{{memory controller
−
|type=LPDDR3-1866  
+
|type=LPDDR3-1866
 +
|type 2=DDR3L-1600
 
|ecc=No
 
|ecc=No
 
|max mem=16 GiB
 
|max mem=16 GiB
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|avx=Yes
 
|avx=Yes
 
|avx2=Yes
 
|avx2=Yes
−
|avx512=No
+
 
 
|abm=Yes
 
|abm=Yes
 
|tbm=No
 
|tbm=No
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|amdvi=No
 
|amdvi=No
 
|amdv=No
 
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 
|rvi=No
 
|rvi=No
 
|smt=No
 
|smt=No

Latest revision as of 16:58, 28 August 2018

Edit Values
Core m5-6Y54
skylake y (front).png
General Info
DesignerIntel
ManufacturerIntel
Model Numberm5-6Y54
Part NumberHE8066201930524
S-SpecSR2EM
MarketMobile
IntroductionSeptember 1, 2015 (announced)
September 27, 2015 (launched)
Release Price$281
ShopAmazon
General Specs
FamilyCore m5
Seriesm-6Y
LockedYes
Frequency1100 MHz
Turbo FrequencyYes
Turbo Frequency2,700 MHz (1 core),
2,400 MHz (2 cores)
Bus typeDMI 3.0
Clock multiplier11
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureSkylake
PlatformSkylake
Core NameSkylake Y
Core Family6
Core Model78
Core SteppingD1
Process14 nm
Transistors1,750,000,000
TechnologyCMOS
Die98.57 mm²
10.3 mm × 9.57 mm
MCPYes (2 dies)
Word Size64 bit
Cores2
Threads4
Max Memory16 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
SDP3 W
TDP4.5 W
cTDP down3.5 W
cTDP down frequency600 MHz
cTDP up7 W
cTDP up frequency1500 MHz
Tjunction5 °C – 100 °C
Packaging
PackageFCBGA-1515 (BGA)
Dimension20 mm × 16.5 mm × 0.5 mm
Pitch0.4 mm
Contacts1515

Core M5-6Y54 is an ultra-low power 64-bit dual-core x86 microprocessor introduced by Intel in late 2015. This MPU operates at 1.1 GHz with a max turbo frequency of 2.7 GHz. This chip, which is manufactured on a 14 nm process, is based on the Skylake microarchitecture. The Core M5-6Y54 incorporates Intel's HD Graphics 515 Gen9 GPU clocked at 300 MHz with turbo frequency of 900 MHz.

Cache[edit]

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associativewrite-back
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  2x256 KiB4-way set associativewrite-back
L3$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
  2x2 MiB write-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR3-1866, DDR3L-1600
Supports ECCNo
Max Mem16 GiB
Controllers1
Channels2
Max Bandwidth27.81 GiB/s
28,477.44 MiB/s
29.861 GB/s
29,860.76 MB/s
0.0272 TiB/s
0.0299 TB/s
Bandwidth
Single 13.91 GiB/s
Double 27.81 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes10
Configs1x4, 2x2, 1x2+2x1, 4x1


Graphics[edit]

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUHD Graphics 515
DesignerIntelDevice ID0x191E
Execution Units24Max Displays3
Max Memory16 GiB
16,384 MiB
16,777,216 KiB
17,179,869,184 B
Frequency300 MHz
0.3 GHz
300,000 KHz
Burst Frequency900 MHz
0.9 GHz
900,000 KHz
OutputDP, eDP, HDMI, DVI
Max Resolution
HDMI4096x2304 @24 Hz
DP3840x2160 @60 Hz
eDP3840x2160 @60 Hz
Standards
DirectX12
OpenGL4.4
OpenCL2.0
DP1.2
eDP1.3
HDMI1.4a
Additional Features
Intel Quick Sync Video
Intel InTru 3D
Intel Clear Video
Intel Clear Video HD

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
MPXMemory Protection Extensions
SGXSoftware Guard Extensions
Secure KeySecure Key Technology
SMEPOS Guard Technology
Flex MemoryFlex Memory Access
ISRTSmart Response Technology
MWTMy WiFi Technology

Drivers[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/core_m/m5-6y54&oldid=81873"
Facts about "Core m5-6Y54 - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Core m5-6Y54 - Intel#io +
base frequency1,100 MHz (1.1 GHz, 1,100,000 kHz) +
bus typeDMI 3.0 +
clock multiplier11 +
core count2 +
core family6 +
core model78 +
core nameSkylake Y +
core steppingD1 +
designerIntel +
device id0x191E +
die area98.57 mm² (0.153 in², 0.986 cm², 98,570,000 µm²) +
die count2 +
die length10.3 mm (1.03 cm, 0.406 in, 10,300 µm) +
die width9.57 mm (0.957 cm, 0.377 in, 9,570 µm) +
drivers urlhttps://downloadcenter.intel.com/product/94026 +
familyCore m5 +
first announcedSeptember 1, 2015 +
first launchedSeptember 27, 2015 +
full page nameintel/core m/m5-6y54 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has ecc memory supportfalse +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Memory Protection Extensions +, Software Guard Extensions +, Secure Key Technology +, OS Guard +, Flex Memory Access +, Smart Response Technology + and My WiFi Technology +
has intel enhanced speedstep technologytrue +
has intel flex memory access supporttrue +
has intel my wifi technology supporttrue +
has intel secure key technologytrue +
has intel smart response technology supporttrue +
has intel supervisor mode execution protectiontrue +
has intel turbo boost technology 2 0true +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
integrated gpuHD Graphics 515 +
integrated gpu base frequency300 MHz (0.3 GHz, 300,000 KHz) +
integrated gpu designerIntel +
integrated gpu execution units24 +
integrated gpu max frequency900 MHz (0.9 GHz, 900,000 KHz) +
integrated gpu max memory16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB) +
is multi-chip packagetrue +
isax86-64 +
isa familyx86 +
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ description8-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description8-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description4-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
ldateSeptember 27, 2015 +
main imageFile:skylake y (front).png +
manufacturerIntel +
market segmentMobile +
max cpu count1 +
max junction temperature373.15 K (100 °C, 212 °F, 671.67 °R) +
max memory16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB, 0.0156 TiB) +
max memory bandwidth27.81 GiB/s (28,477.44 MiB/s, 29.861 GB/s, 29,860.76 MB/s, 0.0272 TiB/s, 0.0299 TB/s) +
max memory channels2 +
max pcie lanes10 +
microarchitectureSkylake +
min junction temperature278.15 K (5 °C, 41 °F, 500.67 °R) +
model numberm5-6Y54 +
nameCore m5-6Y54 +
packageFCBGA-1515 +
part numberHE8066201930524 +
platformSkylake +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 281.00 (€ 252.90, £ 227.61, ¥ 29,035.73) +
s-specSR2EM +
sdp3 W (3,000 mW, 0.00402 hp, 0.003 kW) +
seriesm-6Y +
smp max ways1 +
supported memory typeLPDDR3-1866 + and DDR3L-1600 +
tdp4.5 W (4,500 mW, 0.00603 hp, 0.0045 kW) +
tdp down3.5 W (3,500 mW, 0.00469 hp, 0.0035 kW) +
tdp down frequency600 MHz (0.6 GHz, 600,000 kHz) +
tdp up7 W (7,000 mW, 0.00939 hp, 0.007 kW) +
tdp up frequency1,500 MHz (1.5 GHz, 1,500,000 kHz) +
technologyCMOS +
thread count4 +
transistor count1,750,000,000 +
turbo frequency (1 core)2,700 MHz (2.7 GHz, 2,700,000 kHz) +
turbo frequency (2 cores)2,400 MHz (2.4 GHz, 2,400,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +
x86/has memory protection extensionstrue +
x86/has software guard extensionstrue +