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Difference between revisions of "intel/core i7/i7-820qm"
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{{intel title|Core i7-820QM}} | {{intel title|Core i7-820QM}} | ||
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| name = Intel Core i7-820QM | | name = Intel Core i7-820QM | ||
| image = | | image = | ||
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| locked = Yes | | locked = Yes | ||
| frequency = 1,733.33 MHz | | frequency = 1,733.33 MHz | ||
| − | + | ||
| turbo frequency1 = 3,066.66 MHz | | turbo frequency1 = 3,066.66 MHz | ||
| turbo frequency2 = 2,799.99 MHz | | turbo frequency2 = 2,799.99 MHz | ||
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|avx=No | |avx=No | ||
|avx2=No | |avx2=No | ||
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|abm=No | |abm=No | ||
|tbm=No | |tbm=No | ||
Latest revision as of 15:15, 11 February 2018
| Edit Values | |
| Intel Core i7-820QM | |
| General Info | |
| Designer | Intel |
| Manufacturer | Intel |
| Model Number | i7-820QM |
| Part Number | BY80607002904AK |
| S-Spec | SLBLX |
| Market | Mobile |
| Introduction | June 24, 2009 (announced) September 23, 2009 (launched) |
| Release Price | $546.00 |
| Shop | Amazon |
| General Specs | |
| Family | Core i7 |
| Locked | Yes |
| Frequency | 1,733.33 MHz |
| Turbo Frequency | 3,066.66 MHz (1 core), 2,799.99 MHz (2 cores), 1,866.66 MHz (3 cores), 1,866.66 MHz (4 cores) |
| Bus type | DMI 1.0 |
| Bus rate | 2.5 GT/s |
| Clock multiplier | 13 |
| Microarchitecture | |
| Microarchitecture | Nehalem |
| Platform | Calpella |
| Chipset | Ibex Peak |
| Core Name | Clarksfield |
| Core Family | 6 |
| Core Model | 30 |
| Core Stepping | B1 |
| Process | 45 nm |
| Transistors | 774,000,000 |
| Technology | CMOS |
| Die | 296 mm² |
| Word Size | 64 bit |
| Cores | 4 |
| Threads | 8 |
| Max Memory | 8 GiB |
| Multiprocessing | |
| Max SMP | 1-Way (Uniprocessor) |
| Electrical | |
| Vcore | 1.075 V ± 0.325 V |
| TDP | 45 W |
| Tjunction | 0 °C – 100 °C |
| Tstorage | -25 °C – 125 °C |
Core i7-820QM is a 64-bit x86 quad-core mobile performance microprocessor introduced by Intel late 2009. The processor has a base frequency of 1.73 GHz with a turbo frequency of 3.06 GHz and a TDP of 45 W. This MPU is based on the Clarksfield core (Nehalem microarchitecutre) and is manufactured on Intel's 45 nm process.
Contents
Cache[edit]
- Main article: Nehalem § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options
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Features[edit]
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Facts about "Core i7-820QM - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Core i7-820QM - Intel#io + |
| has ecc memory support | false + |
| has extended page tables support | true + |
| has feature | Hyper-Threading Technology +, Turbo Boost Technology 1.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d + and Extended Page Tables + |
| has intel enhanced speedstep technology | true + |
| has intel trusted execution technology | true + |
| has intel turbo boost technology 1 0 | true + |
| has intel vpro technology | true + |
| has intel vt-d technology | true + |
| has intel vt-x technology | true + |
| has second level address translation support | true + |
| has simultaneous multithreading | true + |
| l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
| l3$ description | 16-way set associative + |
| l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
| max memory bandwidth | 19.87 GiB/s (20,346.88 MiB/s, 21.335 GB/s, 21,335.25 MB/s, 0.0194 TiB/s, 0.0213 TB/s) + |
| max memory channels | 2 + |
| max pcie lanes | 16 + |
| supported memory type | DDR3-1333 + |