From WikiChip
Difference between revisions of "cavium/octeon plus/cn5860-1000bg1521-exp"
m (Bot: Automated text replacement (-\| electrical += Yes +)) |
m (Bot: moving all {{mpu}} to {{chip}}) |
||
(One intermediate revision by the same user not shown) | |||
Line 1: | Line 1: | ||
{{cavium title|CN5860-1000 EXP}} | {{cavium title|CN5860-1000 EXP}} | ||
− | {{ | + | {{chip |
| name = Cavium CN5860-1000 EXP | | name = Cavium CN5860-1000 EXP | ||
| no image = | | no image = | ||
Line 10: | Line 10: | ||
| model number = CN5860-1000 EXP | | model number = CN5860-1000 EXP | ||
| part number = CN5860-1000BG1521-EXP | | part number = CN5860-1000BG1521-EXP | ||
− | |||
| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
+ | | part number 4 = | ||
| market = Network | | market = Network | ||
| first announced = October 9, 2006 | | first announced = October 9, 2006 |
Latest revision as of 15:13, 13 December 2017
Edit Values | |||||||
Cavium CN5860-1000 EXP | |||||||
General Info | |||||||
Designer | Cavium | ||||||
Manufacturer | TSMC | ||||||
Model Number | CN5860-1000 EXP | ||||||
Part Number | CN5860-1000BG1521-EXP | ||||||
Market | Network | ||||||
Introduction | October 9, 2006 (announced) February, 2007 (launched) | ||||||
General Specs | |||||||
Family | OCTEON Plus | ||||||
Series | CN58xx | ||||||
Frequency | 1,000 MHz | ||||||
Microarchitecture | |||||||
ISA | MIPS64 (MIPS) | ||||||
Microarchitecture | cnMIPS | ||||||
Process | 90 nm | ||||||
Technology | CMOS | ||||||
Word Size | 64 bit | ||||||
Cores | 16 | ||||||
Threads | 16 | ||||||
Multiprocessing | |||||||
Max SMP | 1-Way (Uniprocessor) | ||||||
Electrical | |||||||
Power dissipation | 40 W | ||||||
Packaging | |||||||
|
CN5860-1000 EXP is a 64-bit hexadeca-core MIPS network microprocessor designed by Cavium and introduced in 2007. This processor, which incorporates sixteen cnMIPS cores, operates at 1 GHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of various software such as RegEx, compression/decompression, and TCP acceleration.
Contents
Cache[edit]
- Main article: cnMIPS § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
|||||||||||||||||||||||||
|
Memory controller[edit]
Integrated Memory Controller
|
||||||||||||||
|
Expansions[edit]
Expansion Options
|
||||||||||||||||
|
Networking[edit]
Networking
|
||||||||
|
Hardware Accelerators[edit]
[Edit/Modify Accelerators Info]
Hardware Accelerators
|
||||||||||||||||||
|
Block diagram[edit]
Datasheet[edit]
Facts about "CN5860-1000 EXP - Cavium"
has ecc memory support | true + |
has hardware accelerators for data compression | true + |
has hardware accelerators for data decompression | true + |
has hardware accelerators for network quality of service processing | true + |
has hardware accelerators for regular expression | true + |
has hardware accelerators for tcp packet processing | true + |
l1$ size | 768 KiB (786,432 B, 0.75 MiB) + |
l1d$ description | 64-way set associative + |
l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1i$ description | 64-way set associative + |
l1i$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + |
max memory channels | 1 + |
supported memory type | DDR2-800 + |