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Difference between revisions of "pezy/pezy-scx/pezy-sc4"
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{{pezy title|PEZY-SC4}}
 
{{pezy title|PEZY-SC4}}
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{{mpu
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{{chip
 
|future=Yes
 
|future=Yes
 
|name=PEZY-SC4
 
|name=PEZY-SC4
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|designer=PEZY
 
|designer=PEZY
 
|manufacturer=TSMC
 
|manufacturer=TSMC
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|model number=PEZY-SC2
+
|model number=PEZY-SC4
 
|market=Supercomputer
 
|market=Supercomputer
 
|first announced=2016
 
|first announced=2016
 
|first launched=2020
 
|first launched=2020
 +
|family=PEZY-SCx
 
|frequency=1,600 MHz
 
|frequency=1,600 MHz
 
|process=5 nm
 
|process=5 nm
 
|technology=CMOS
 
|technology=CMOS
 
|die area=740 mm²
 
|die area=740 mm²
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|core count=16,192
+
|core count=16,384
 +
|thread count=131,072
 
|power=640 W
 
|power=640 W
 
|v core=0.55 V
 
|v core=0.55 V
 
}}
 
}}
−
'''PEZY-SC4''' ('''PEZY Super Computer 4''') is fifth generation [[many-core microprocessor]] planned by [[PEZY]]. The SC4 incorporates 16,192 cores, twice times as many cores as its predecessor.
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'''PEZY-SC4''' ('''PEZY Super Computer 4''') is a fifth generation [[many-core microprocessor]] developed by [[PEZY]] set to be introduced in the early-2020s. This chip, which is planned to operate at 1.6 GHz, will incorporate 16,384 cores and dissipate 640 W. The PEZY-SC4 will power the [[ZettaScaler]]-4.x series of supercomputers.
  
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Planned to be fabricated on TSMC's [[5 nm process]], PEZY-SC5 operates at 1.6 GHz and consume around 640 W while delivering performance in the order of 210 TFLOPS (HP), 105 TFLOPS (SP), and 52.5 TFLOPS (DP).
 
  
 +
{{unknown features}}
  
  
−
{{unknown features}}
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== Overview ==
 +
The SC4 will be introduced by [[PEZY]] along with their fourth-generation [[ZettaScaler]]-4.0 supercomputer series. The SC4 is set to incorporate 16,384 cores along with 8-way [[simultaneous multithreading|SMT]] support for a total of 131,072 threads, twice as many cores as {{\\|PEZY-SC3|its predecessor}}.
 +
 
 +
Operating at 1.6 GHz, the PEZY-SC4 will have a peak performance of 105 TFLOPS (single-precision) and 52.5 TFLOPS (double-precision) while consuming around 640 Watts. The PEZY-SC4 is expected to be manufactured on [[TSMC]]'s [[5 nm process]].
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{{#set:
 +
| peak flops (half-precision)  = {{#expr:1600000000 * 8 * 16384}} FLOPS
 +
| peak flops (single-precision) = {{#expr:1600000000 * 4 * 16384}} FLOPS
 +
| peak flops (double-precision) = {{#expr:1600000000 * 2 * 16384}} FLOPS
 +
}}
  
 +
== Cache ==
 +
{{empty section}}
  
 
== Memory controller ==
 
== Memory controller ==
 +
For main memory, the PEZY-SC4 supports 4 channels of 64-bit DDR5-4000 memory with ECC support for a total aggregated bandwidth of 107.3 GiB/s
 
{{memory controller
 
{{memory controller
 
|type=DDR5-4000
 
|type=DDR5-4000
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|controllers=4
 
|controllers=4
 
|channels=4
 
|channels=4
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|width=64 bit
 
|max bandwidth=119.2 GiB/s
 
|max bandwidth=119.2 GiB/s
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|bandwidth schan=29.8 GiB/s
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|bandwidth dchan=59.6 GiB/s
 
|bandwidth qchan=119.2 GiB/s
 
|bandwidth qchan=119.2 GiB/s
 
}}
 
}}
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 +
In addition to main memory bandwidth, the PEZY-SC4 supports Wide-IO with a width of 4,096 bit, twice of the {{\\|PEZY-SC3|SC3}}. As with the SC3, the SC4 will use [[ThruChip Interface]] (TCI) interfaces in order to communicate with the TCI-DRAM chips. This chip incorporates 8 interfaces, operating at 3 GHz for a bandwidth of 2.8 TiB/s per interface for a total aggregated bandwidth of 22.35 TB/s - twice the bandwidth of its predecessor.
  
 
{{memory controller
 
{{memory controller
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|max bandwidth=22.35 TiB/s
 
|max bandwidth=22.35 TiB/s
 
}}
 
}}
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== Expansions ==
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With the SC4, PEZY plans to expand on the custom optics interface that was designed for the {{\\|PEZY-SC3}} for up to 512 lanes.

Latest revision as of 14:12, 21 April 2018

Edit Values
PEZY-SC4
General Info
DesignerPEZY
ManufacturerTSMC
Model NumberPEZY-SC4
MarketSupercomputer
Introduction2016 (announced)
2020 (launched)
General Specs
FamilyPEZY-SCx
Frequency1,600 MHz
Microarchitecture
Process5 nm
TechnologyCMOS
Die740 mm²
Cores16,384
Threads131,072
Electrical
Power dissipation640 W
Vcore0.55 V

PEZY-SC4 (PEZY Super Computer 4) is a fifth generation many-core microprocessor developed by PEZY set to be introduced in the early-2020s. This chip, which is planned to operate at 1.6 GHz, will incorporate 16,384 cores and dissipate 640 W. The PEZY-SC4 will power the ZettaScaler-4.x series of supercomputers.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.


Overview[edit]

The SC4 will be introduced by PEZY along with their fourth-generation ZettaScaler-4.0 supercomputer series. The SC4 is set to incorporate 16,384 cores along with 8-way SMT support for a total of 131,072 threads, twice as many cores as its predecessor.

Operating at 1.6 GHz, the PEZY-SC4 will have a peak performance of 105 TFLOPS (single-precision) and 52.5 TFLOPS (double-precision) while consuming around 640 Watts. The PEZY-SC4 is expected to be manufactured on TSMC's 5 nm process.


Cache[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Memory controller[edit]

For main memory, the PEZY-SC4 supports 4 channels of 64-bit DDR5-4000 memory with ECC support for a total aggregated bandwidth of 107.3 GiB/s

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR5-4000
Supports ECCYes
Controllers4
Channels4
Width64 bit
Max Bandwidth119.2 GiB/s
122,060.8 MiB/s
127.99 GB/s
127,990.025 MB/s
0.116 TiB/s
0.128 TB/s
Bandwidth
Single 29.8 GiB/s
Double 59.6 GiB/s
Quad 119.2 GiB/s

In addition to main memory bandwidth, the PEZY-SC4 supports Wide-IO with a width of 4,096 bit, twice of the SC3. As with the SC3, the SC4 will use ThruChip Interface (TCI) interfaces in order to communicate with the TCI-DRAM chips. This chip incorporates 8 interfaces, operating at 3 GHz for a bandwidth of 2.8 TiB/s per interface for a total aggregated bandwidth of 22.35 TB/s - twice the bandwidth of its predecessor.

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
MemoryWide I/O
Rate3,000 MHz
Width4,096 bit
Channels8
Max Bandwidth22.35 TiB/s
22,886.4 GiB/s
23,435,673.6 MiB/s
24,574.085 GB/s
24,574,084.881 MB/s
24.574 TB/s

Expansions[edit]

With the SC4, PEZY plans to expand on the custom optics interface that was designed for the PEZY-SC3 for up to 512 lanes.

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Facts about "PEZY-SC4 - PEZY"
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PEZY-SC4 - PEZY#io +
has ecc memory supporttrue + and false +
max memory bandwidth119.2 GiB/s (122,060.8 MiB/s, 127.99 GB/s, 127,990.025 MB/s, 0.116 TiB/s, 0.128 TB/s) + and 22,886.4 GiB/s (23,435,673.6 MiB/s, 24,574.085 GB/s, 24,574,084.881 MB/s, 22.35 TiB/s, 24.574 TB/s) +
max memory channels4 + and 8 +
max pcie lanes512 +
supported memory typeDDR5-4000 +