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{{pezy title|PEZY-1}} | {{pezy title|PEZY-1}} | ||
− | {{ | + | {{chip |
− | | name | + | |name=PEZY-1 |
− | | | + | |image=pezy 1.jpg |
− | + | |designer=PEZY | |
− | + | |manufacturer=TSMC | |
− | + | |model number=PEZY-1 | |
− | | designer | + | |market=Industrial |
− | | manufacturer | + | |first announced=2011 |
− | | model number | + | |first launched=2012 |
− | + | |frequency=533.33 MHz | |
− | | market | + | |process=40 nm |
− | | first announced | + | |technology=CMOS |
− | | first launched | + | |die area=335 mm² |
− | + | |die length=16.8 mm | |
− | + | |die width=21 mm | |
− | + | |core count=512 | |
− | + | |power=35 W | |
− | + | |tjunc min=<!-- °C --> | |
− | + | |electrical=Yes | |
− | | frequency | + | |packaging=Yes |
− | + | |package 0=fcBGA-1517 | |
− | + | |package 0 type=fcBGA | |
− | + | |package 0 pins=1517 | |
− | + | |package 0 pitch=1 mm | |
− | + | |package 0 width=40 mm | |
− | + | |package 0 length=40 mm | |
− | + | |package 0 height=3.01 mm | |
− | + | |socket 0=BGA-1517 | |
− | + | |socket 0 type=BGA | |
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− | | process | ||
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− | | technology | ||
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− | | die length | ||
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− | | core count | ||
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− | | power | ||
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− | | tjunc min | ||
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− | | packaging | ||
− | | package 0 | ||
− | | package 0 type | ||
− | | package 0 pins | ||
− | | package 0 pitch | ||
− | | package 0 width | ||
− | | package 0 length | ||
− | | package 0 height | ||
− | | socket 0 | ||
− | | socket 0 type | ||
}} | }} | ||
− | '''PEZY-1''' was a first generation [[many-core microprocessor]] developed by [[PEZY]] in 2012. PEZY-1 contains 2 {{armh|ARM926}} cores ({{arm|ARMv5TEJ}}) along with 512 simpler RISC cores. Operating at 533 MHz, the processor is said to have | + | '''PEZY-1''' was a first generation [[many-core microprocessor]] developed by [[PEZY]] in 2012. PEZY-1 contains 2 {{armh|ARM926}} cores ({{arm|ARMv5TEJ}}) along with 512 simpler RISC cores. Operating at 533 MHz, the processor is said to have peak performance of 533 GFLOPS (single-precision) and 266 GFLOPS (double-precision). PEZY-1 was designed using 220 million gates and manufactured on TSMC's [[40 nm process]]. |
− | The PEZY-1 is used for image processing devices and various medical instruments. In 2014 PEZY introduced their second generation many-core processor, the {{pezy|PEZY-SC}}, with twice as many cores. | + | The PEZY-1 is used for image processing devices and various medical instruments. In 2014 PEZY introduced their second generation many-core processor, the {{pezy|PEZY-SC}}, with twice as many cores and formed the basis for the {{pezy|PEZY-SCx}} family. |
== Cache == | == Cache == | ||
− | PEZY-1's cache is separate from the {{armh|ARM926}}'s cache which has an L1$ of | + | PEZY-1's cache is separate from the {{armh|ARM926}}'s cache which has an L1$ of 16 KiB (2x) and no L2$. |
− | {{cache | + | {{cache size |
|l1 cache=128 KiB | |l1 cache=128 KiB | ||
+ | |l1i cache=64 KiB | ||
+ | |l1i break=1x64 KiB | ||
+ | |l1d cache=64 KiB | ||
+ | |l1d break=1x64 KiB | ||
|l2 cache=1 MiB | |l2 cache=1 MiB | ||
− | | | + | |l2 break=1x1 MiB |
− | |||
}} | }} | ||
== Memory controller == | == Memory controller == | ||
− | {{ | + | {{memory controller |
− | | type | + | |type=DDR3-1333 |
− | | controllers | + | |ecc=Yes |
− | | channels | + | |controllers=4 |
− | | | + | |channels=4 |
− | | bandwidth | + | |width=64 bit |
− | | bandwidth | + | |max bandwidth=39.74 GiB/s |
− | | bandwidth | + | |bandwidth schan=9.93 GiB/s |
− | | | + | |bandwidth dchan=19.86 GiB/s |
+ | |bandwidth qchan=39.74 GiB/ | ||
}} | }} | ||
== Expansions == | == Expansions == | ||
− | {{ | + | {{expansions |
| pcie revision = 2.0 | | pcie revision = 2.0 | ||
− | | pcie lanes = | + | | pcie lanes = 24 |
− | | pcie config = | + | | pcie config = 6x4 |
− | + | | uart = Yes | |
− | + | | gp io = Yes | |
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− | | uart = | ||
− | | gp io = | ||
}} | }} | ||
== PEZY-1 Quad PCI Board == | == PEZY-1 Quad PCI Board == | ||
[[File:pezy 1 quad pci board.jpg|200px|right]] | [[File:pezy 1 quad pci board.jpg|200px|right]] | ||
− | PEZY has developed a Quad-PEZY-1 PCI board for their microprocessors which has 4 PEZY-1 for a total of 2,048 PE cores (along with 8 ARM cores). The board is equipped with 64 | + | PEZY has developed a Quad-PEZY-1 PCI board for their microprocessors which has 4 PEZY-1 for a total of 2,048 PE cores (along with 8 ARM cores). The board is equipped with 64 GiB of memory for a total bandwidth of 200 GB/s. PEZY reports the total computational power for the board to be at 2.56 TFLOPS with a power consumption of 180 Watts. |
== Documents == | == Documents == | ||
* [[:File:pezy 1 board.pdf|PEZY-1 Board]] | * [[:File:pezy 1 board.pdf|PEZY-1 Board]] | ||
* [[:File:PEZY Computing (February 20, 2015).pdf|PEZY Computing (February 20, 2015)]] | * [[:File:PEZY Computing (February 20, 2015).pdf|PEZY Computing (February 20, 2015)]] |
Latest revision as of 03:48, 20 October 2018
Edit Values | |
PEZY-1 | |
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General Info | |
Designer | PEZY |
Manufacturer | TSMC |
Model Number | PEZY-1 |
Market | Industrial |
Introduction | 2011 (announced) 2012 (launched) |
General Specs | |
Frequency | 533.33 MHz |
Microarchitecture | |
Process | 40 nm |
Technology | CMOS |
Die | 335 mm² 16.8 mm × 21 mm |
Cores | 512 |
Electrical | |
Power dissipation | 35 W |
PEZY-1 was a first generation many-core microprocessor developed by PEZY in 2012. PEZY-1 contains 2 ARM926 cores (ARMv5TEJ) along with 512 simpler RISC cores. Operating at 533 MHz, the processor is said to have peak performance of 533 GFLOPS (single-precision) and 266 GFLOPS (double-precision). PEZY-1 was designed using 220 million gates and manufactured on TSMC's 40 nm process.
The PEZY-1 is used for image processing devices and various medical instruments. In 2014 PEZY introduced their second generation many-core processor, the PEZY-SC, with twice as many cores and formed the basis for the PEZY-SCx family.
Cache[edit]
PEZY-1's cache is separate from the ARM926's cache which has an L1$ of 16 KiB (2x) and no L2$.
![]() |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options
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PEZY-1 Quad PCI Board[edit]
PEZY has developed a Quad-PEZY-1 PCI board for their microprocessors which has 4 PEZY-1 for a total of 2,048 PE cores (along with 8 ARM cores). The board is equipped with 64 GiB of memory for a total bandwidth of 200 GB/s. PEZY reports the total computational power for the board to be at 2.56 TFLOPS with a power consumption of 180 Watts.
Documents[edit]
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | PEZY-1 - PEZY#io + |
base frequency | 533.33 MHz (0.533 GHz, 533,330 kHz) + |
core count | 512 + |
designer | PEZY + |
die area | 335 mm² (0.519 in², 3.35 cm², 335,000,000 µm²) + |
die length | 16.8 mm (1.68 cm, 0.661 in, 16,800 µm) + |
die width | 21 mm (2.1 cm, 0.827 in, 21,000 µm) + |
first announced | 2011 + |
first launched | 2012 + |
full page name | pezy/pezy-1 + |
has ecc memory support | true + |
instance of | microprocessor + |
l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
ldate | 2012 + |
main image | ![]() |
manufacturer | TSMC + |
market segment | Industrial + |
max memory bandwidth | 39.74 GiB/s (40,693.76 MiB/s, 42.671 GB/s, 42,670.5 MB/s, 0.0388 TiB/s, 0.0427 TB/s) + |
max memory channels | 4 + |
max pcie lanes | 24 + |
model number | PEZY-1 + |
name | PEZY-1 + |
power dissipation | 35 W (35,000 mW, 0.0469 hp, 0.035 kW) + |
process | 40 nm (0.04 μm, 4.0e-5 mm) + |
supported memory type | DDR3-1333 + |
technology | CMOS + |