From WikiChip
Difference between revisions of "amd/duron/d850aut1b"
m (Bot: corrected mem) |
m (Bot: moving all {{mpu}} to {{chip}}) |
||
(5 intermediate revisions by 2 users not shown) | |||
Line 1: | Line 1: | ||
{{amd title|Duron 850 (Spitfire)}} | {{amd title|Duron 850 (Spitfire)}} | ||
− | {{ | + | {{chip |
| name = Duron 850 | | name = Duron 850 | ||
| no image = Yes | | no image = Yes | ||
Line 10: | Line 10: | ||
| model number = Duron 850 | | model number = Duron 850 | ||
| part number = D850AUT1B | | part number = D850AUT1B | ||
− | | part number | + | | part number 2 = D0850AUT1B |
− | |||
| part number 3 = | | part number 3 = | ||
+ | | part number 4 = | ||
| market = Desktop | | market = Desktop | ||
| first announced = January 8, 2001 | | first announced = January 8, 2001 | ||
Line 47: | Line 47: | ||
| max memory = 4 GiB | | max memory = 4 GiB | ||
− | + | ||
| power = | | power = | ||
| v core = 1.6 V | | v core = 1.6 V | ||
Line 106: | Line 106: | ||
== Features == | == Features == | ||
− | {{ | + | {{x86 features |
| em64t = | | em64t = | ||
| nx = | | nx = |
Latest revision as of 16:07, 13 December 2017
Edit Values | |
Duron 850 | |
General Info | |
Designer | AMD |
Manufacturer | AMD |
Model Number | Duron 850 |
Part Number | D850AUT1B, D0850AUT1B |
Market | Desktop |
Introduction | January 8, 2001 (announced) January 8, 2001 (launched) |
Shop | Amazon |
General Specs | |
Family | Duron |
Series | Duron Desktop |
Locked | Yes |
Frequency | 850 MHz |
Bus type | FSB |
Bus speed | 100 MHz |
Bus rate | 200 MT/s |
Clock multiplier | 8.5 |
CPUID | 630 |
Microarchitecture | |
Microarchitecture | K7 |
Core Name | Spitfire |
Core Family | 6 |
Core Model | 3 |
Core Stepping | 0 |
Process | 180 nm |
Transistors | 25,000,000 |
Technology | CMOS |
Die | 100 mm² |
Word Size | 32 bit |
Cores | 1 |
Threads | 1 |
Max Memory | 4 GiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
Vcore | 1.6 V ± 0.1 V |
TDP | 37.4 W |
Tcase | 0 °C – 90 °C |
Tstorage | -40 °C – 100 °C |
Duron 850 based on the Spitfire core was a 32-bit x86 microprocessor developed by AMD and introduced in 2001. This model was part of the first series of the Duron family. Designed based on AMD's K7 (a Thunderbird-derivative) on a 180 nm process, this MPU operated at 850 MHz with a bus capable of 200 MT/s with a typical TDP of 37.4 W.
Cache[edit]
- Main article: K7 § Cache
Cache Info [Edit Values] | ||
L1I$ | 64 KiB 65,536 B 0.0625 MiB |
1x64 KiB 2-way set associative |
L1D$ | 64 KiB 65,536 B 0.0625 MiB |
1x64 KiB 2-way set associative |
L2$ | 64 KiB 0.0625 MiB 65,536 B 6.103516e-5 GiB |
1x64 KiB 16-way set associative |
Graphics[edit]
This SoC has no integrated graphics processing unit.
Features[edit]
[Edit/Modify Supported Features]
![]() |
Supported x86 Extensions & Processor Features
|
|||||||
|
- Halt State
- Sleep State
Documents[edit]
DataSheet[edit]
- AMD Duron Processor Model 3 Data Sheet; Publication # 23802; Rev: I; Issue Date: June 2001.
Other[edit]
- AMD Duron Processor Model 3 Revision Guide; Publication # 23865; Rev: K; Issue Date: October 2003.
Facts about "Duron 850 (Spitfire) - AMD"
has feature | Halt State + and Sleep State + |
l1d$ description | 2-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 2-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) + |