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Difference between revisions of "cavium/octeon plus/cn5750-900bg1217-sp"
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{{cavium title|CN5750-900 SP}} | {{cavium title|CN5750-900 SP}} | ||
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| name = Cavium CN5750-900 SP | | name = Cavium CN5750-900 SP | ||
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| model number = CN5750-900 SP | | model number = CN5750-900 SP | ||
| part number = CN5750-900BG1217-SP | | part number = CN5750-900BG1217-SP | ||
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| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
| + | | part number 4 = | ||
| market = Storage | | market = Storage | ||
| first announced = Jun 26, 2007 | | first announced = Jun 26, 2007 | ||
Latest revision as of 15:12, 13 December 2017
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| Cavium CN5750-900 SP | |||||||||
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| General Info | |||||||||
| Designer | Cavium | ||||||||
| Manufacturer | TSMC | ||||||||
| Model Number | CN5750-900 SP | ||||||||
| Part Number | CN5750-900BG1217-SP | ||||||||
| Market | Storage | ||||||||
| Introduction | Jun 26, 2007 (announced) August, 2007 (launched) | ||||||||
| General Specs | |||||||||
| Family | OCTEON Plus | ||||||||
| Series | CN57xx | ||||||||
| Frequency | 900 MHz | ||||||||
| Microarchitecture | |||||||||
| ISA | MIPS64 (MIPS) | ||||||||
| Microarchitecture | cnMIPS | ||||||||
| Process | 90 nm | ||||||||
| Technology | CMOS | ||||||||
| Word Size | 64 bit | ||||||||
| Cores | 12 | ||||||||
| Threads | 12 | ||||||||
| Multiprocessing | |||||||||
| Max SMP | 1-Way (Uniprocessor) | ||||||||
| Packaging | |||||||||
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CN5750-900 SP is a 64-bit dodeca-core MIPS storage processor (SP) designed by Cavium and introduced in 2007. This processor, which incorporates twelve cnMIPS cores, operates at 900 MHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as RAID, networking, TCP & QoS acceleration.
Contents
Cache[edit]
- Main article: cnMIPS § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options
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Networking[edit]
Interface options:
- 8-lanes PCIe + 8-lanes PCIe
- 8-lanes PCIe + 4 lanes PCIe + 4x [SGMII OR XAUI]
- 2x [4-lanes PCIe] + 2x [4x SGMII OR XAUI]
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Networking
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Hardware Accelerators[edit]
[Edit/Modify Accelerators Info]
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Hardware Accelerators
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Block diagram[edit]
Datasheet[edit]
Facts about "CN5750-900 SP - Cavium"
