From WikiChip
Difference between revisions of "amd/epyc/7251"
< amd‎ | epyc

(Replaced package module by package name.)
 
(11 intermediate revisions by 3 users not shown)
Line 1: Line 1:
 
{{amd title|EPYC 7251}}
 
{{amd title|EPYC 7251}}
−
{{mpu
+
{{chip
−
|future=Yes
 
 
|name=EPYC 7251
 
|name=EPYC 7251
 
|no image=Yes
 
|no image=Yes
Line 8: Line 7:
 
|model number=7251
 
|model number=7251
 
|part number=PS7251BFV8SAF
 
|part number=PS7251BFV8SAF
 +
|part number 2=PS7251BFAFWOF
 
|market=Server
 
|market=Server
 
|first announced=June 20, 2017
 
|first announced=June 20, 2017
 +
|first launched=June 20, 2017
 +
|release price=$574
 
|family=EPYC
 
|family=EPYC
 
|series=7000
 
|series=7000
Line 29: Line 31:
 
|core family=23
 
|core family=23
 
|core model=1
 
|core model=1
−
|core stepping=2
+
|core stepping=B2
 
|process=14 nm
 
|process=14 nm
 
|transistors=19,200,000,000
 
|transistors=19,200,000,000
 
|technology=CMOS
 
|technology=CMOS
−
|die area=195.228 mm²
+
|die area=213 mm²
−
|die length=8.87 mm
 
−
|die width=22.01 mm
 
 
|mcp=Yes
 
|mcp=Yes
 
|die count=4
 
|die count=4
Line 44: Line 44:
 
|max memory=2 TiB
 
|max memory=2 TiB
 
|tdp=120 W
 
|tdp=120 W
−
|package module 1={{packages/amd/socket sp3}}
+
|tcase min=0 °C
 +
|tcase max=81 °C
 +
|package name 1=amd,socket_sp3
 
}}
 
}}
 
'''EPYC 7251''' is a dual-socket {{arch|64}} [[octa-core]] [[x86]] enterprise server microprocessor introduced by [[AMD]] in mid-[[2017]]. This processor is based on the {{amd|Zen|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. The 7251 has a base frequency of 2.1 GHz with a turbo frequency of 2.9 GHz for all cores. This chip has a TDP of 120 W and supports up to 2 TiB of octa-channel DDR4-2400 ECC memory per socket.
 
'''EPYC 7251''' is a dual-socket {{arch|64}} [[octa-core]] [[x86]] enterprise server microprocessor introduced by [[AMD]] in mid-[[2017]]. This processor is based on the {{amd|Zen|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. The 7251 has a base frequency of 2.1 GHz with a turbo frequency of 2.9 GHz for all cores. This chip has a TDP of 120 W and supports up to 2 TiB of octa-channel DDR4-2400 ECC memory per socket.
Line 66: Line 68:
 
|l2 desc=8-way set associative
 
|l2 desc=8-way set associative
 
|l2 policy=write-back
 
|l2 policy=write-back
−
|l3 cache=64 MiB
+
|l3 cache=32 MiB
−
|l3 break=8x8 MiB
+
|l3 break=4x8 MiB
 
|l3 desc=16-way set associative
 
|l3 desc=16-way set associative
 
}}
 
}}
Line 127: Line 129:
 
|avx=Yes
 
|avx=Yes
 
|avx2=Yes
 
|avx2=Yes
−
|avx512=No
+
 
 
|abm=Yes
 
|abm=Yes
 
|tbm=No
 
|tbm=No
Line 172: Line 174:
 
|amdvi=Yes
 
|amdvi=Yes
 
|amdv=Yes
 
|amdv=Yes
 +
|amdsme=Yes
 +
|amdtsme=Yes
 +
|amdsev=Yes
 
|rvi=No
 
|rvi=No
 
|smt=Yes
 
|smt=Yes

Latest revision as of 11:36, 18 March 2023

Edit Values
EPYC 7251
General Info
DesignerAMD
ManufacturerGlobalFoundries
Model Number7251
Part NumberPS7251BFV8SAF,
PS7251BFAFWOF
MarketServer
IntroductionJune 20, 2017 (announced)
June 20, 2017 (launched)
Release Price$574
ShopAmazon
General Specs
FamilyEPYC
Series7000
LockedNo
Frequency2,100 MHz
Turbo Frequency2,900 MHz (1 core),
2,900 MHz (2 cores),
2,900 MHz (3 cores),
2,900 MHz (4 cores),
2,900 MHz (5 cores),
2,900 MHz (6 cores),
2,900 MHz (7 cores),
2,900 MHz (8 cores)
Clock multiplier21
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureZen
Core NameNaples
Core Family23
Core Model1
Core SteppingB2
Process14 nm
Transistors19,200,000,000
TechnologyCMOS
Die213 mm²
MCPYes (4 dies)
Word Size64 bit
Cores8
Threads16
Max Memory2 TiB
Multiprocessing
Max SMP2-Way (Multiprocessor)
Electrical
TDP120 W
Tcase0 °C – 81 °C
Packaging
PackageSP3, FCLGA-4094 (FC-OLGA)
Dimension75.4 mm × 58.5 mm × 6.26 mm
Pitch0.87 mm × 1 mm
Contacts4094
SocketSP3, LGA-4094

EPYC 7251 is a dual-socket 64-bit octa-core x86 enterprise server microprocessor introduced by AMD in mid-2017. This processor is based on the Zen microarchitecture and is manufactured on a 14 nm process. The 7251 has a base frequency of 2.1 GHz with a turbo frequency of 2.9 GHz for all cores. This chip has a TDP of 120 W and supports up to 2 TiB of octa-channel DDR4-2400 ECC memory per socket.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache[edit]

Main article: Zen § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$768 KiB
786,432 B
0.75 MiB
L1I$512 KiB
524,288 B
0.5 MiB
8x64 KiB4-way set associative 
L1D$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associativewrite-back
L2$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
  8x512 KiB8-way set associativewrite-back
L3$32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
  4x8 MiB16-way set associative 

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2400
Supports ECCYes
Max Mem2 TiB
Controllers8
Channels8
Max Bandwidth143.1 GiB/s
146,534.4 MiB/s
153.652 GB/s
153,652.455 MB/s
0.14 TiB/s
0.154 TB/s
Bandwidth
Single 17.88 GiB/s
Double 35.76 GiB/s
Quad 71.53 GiB/s
Hexa 107.3 GiB/s
Octa 143.1 GiB/s

In a dual-socket configuration, the maximum supported memory doubles to 4 TiB along with the maximum theoretical bandwidth of 286.2 GiB/s.

Expansions[edit]

The EPYC 7351P has 128 Gen 3 PCIe lanes.

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes128
Configs8x16, 32x4


Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
SSE4aStreaming SIMD Extensions 4a
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
SHASHA Extensions
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
SMTSimultaneous Multithreading
AMD-ViAMD-Vi (I/O MMU virtualization)
AMD-VAMD Virtualization
SMESecure Memory Encryption
TSMETransparent SME
SEVSecure Encrypted Virtualization
SenseMISenseMI Technology
Retrieved from "https://en.wikichip.org/w/index.php?title=amd/epyc/7251&oldid=101308"
Facts about "EPYC 7251 - AMD"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
EPYC 7251 - AMD#io +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has amd amd-v technologytrue +
has amd amd-vi technologytrue +
has amd sensemi technologytrue +
has ecc memory supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension + and SenseMI Technology +
has simultaneous multithreadingtrue +
has x86 advanced encryption standard instruction set extensiontrue +
l1$ size768 KiB (786,432 B, 0.75 MiB) +
l1d$ description8-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description4-way set associative +
l1i$ size512 KiB (524,288 B, 0.5 MiB) +
l2$ description8-way set associative +
l2$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l3$ description16-way set associative +
l3$ size64 MiB (65,536 KiB, 67,108,864 B, 0.0625 GiB) +
max memory bandwidth143.1 GiB/s (146,534.4 MiB/s, 153.652 GB/s, 153,652.455 MB/s, 0.14 TiB/s, 0.154 TB/s) +
max memory channels8 +
max pcie lanes128 +
supported memory typeDDR4-2400 +