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|designer=DEC
 
|designer=DEC
 
|manufacturer=DEC
 
|manufacturer=DEC
−
|introduction=November 20 1992
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|introduction=November 20, 1992
 
|process=0.75 µm
 
|process=0.75 µm
 
|process 2=0.675 µm
 
|process 2=0.675 µm
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== Etymology ==
 
== Etymology ==
−
The microarchitecture name '''Alpha 21064''' is composed of both the [[ISA]] and the [[microarchitecture|implementation]]. In particular, the "Alpha" refers to [[DEC]]'s [[Alpha AXP]] instruction set architecture while the "21064" refers to a "21st century"-ready {{arch|64}} "0th generation" microarchitecture.
+
The microarchitecture name '''Alpha 21064''' is composed of both the [[ISA]] and the [[microarchitecture|implementation]]. In particular, the "Alpha" refers to [[DEC]]'s [[Alpha AXP]] instruction set architecture while the "21064" refers to a "21st century"-ready {{arch|64}} "generation 0" microarchitecture.
 +
 
 +
Initial test chips were called '''EV-3''' (Extended VAX on CMOS-3) whereas the final chips were called '''EV-4''' (Extended VAX on CMOS-4).
  
 
== Release Dates ==
 
== Release Dates ==
−
DEC first announced their 21064 architecture in February of [[1992]]. Alpha 21064-based chips were first introduced during [[COMDEX]] on November 20, 1992.
+
Tape-out for the Alpha 21064 occurred on July 14, [[1991]]. First parts were available on August 30 and a successful boot-up took place on November 3 the same year. DEC first announced their 21064 architecture in February of [[1992]]. Alpha 21064-based chips were first introduced during [[COMDEX]] on November 20, 1992.
  
 
== Process Technology ==
 
== Process Technology ==
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== Architecture ==
 
== Architecture ==
−
{{empty section}}
+
The 21064 was designed to be a very fast implementation of [[DEC]]'s [[Alpha]]
 +
 
 +
* [[0.75 µm process]]
 +
* 150-200 MHz (6.6-5 ns cycles)
 +
* FP Unit
 +
** Support for [[IEEE 754]]
 +
** Support for VAX floating point
 +
* System bus
 +
** Separate data & address buses
 +
** 64/128-bit data bus
 +
* Directly serial ROM interface
 +
* Pipeline
 +
** 2-way instruction issue to A-/E-/F- Boxes
 +
** Integer Execution Unit
 +
*** 32-entry integer register file
 +
*** 64-bit integers operations
 +
*** 7-stage pipeline
 +
** FP Execution Unit
 +
*** 32-entry FP register file
 +
*** 10-stage pipeline
 +
* Memory subsystem
 +
** 4-entry, 32-byte/entry write buffer
 +
 
 +
=== Memory Hierarchy ===
 +
* Cache
 +
** L1D Cache:
 +
*** 8 KiB direct-mapped
 +
*** 32-byte line size
 +
*** 32-byte fill
 +
*** write-through policy
 +
** L1I Cache:
 +
*** 8 KiB direct-mapped
 +
*** 32-byte line size
 +
*** 32-byte fill
 +
*** 64 {{alpha|ASN}}s
 +
** L2 Cache:
 +
*** 0.125-16 MiB
 +
*** Implemented externally on the motherboard
 +
*** Direct on-chip pin interface
 +
** DRAM
 +
*** Virtual address size
 +
**** 64-bit, 43-bit implemented
 +
*** Physical address size
 +
**** 34-bit implemented
 +
 
 +
Alpha 21064 TLB consists of dedicated level one TLB for instruction cache and another one for data cache.
 +
 
 +
* TLBs
 +
** ITLB
 +
*** 8 KiB, 64 KiB, 256 KiB, 4 MiB page sizes
 +
*** 32-entry, fully-associative
 +
** DTLB
 +
*** 8 KiB page translations:
 +
**** 8-entry, fully-associative
 +
*** 4 MiB page translations:
 +
**** 4-entry, fully-associative
  
 
== Die ==
 
== Die ==
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* [[0.75 µm process]]
 
* [[0.75 µm process]]
 
* 3 metal layers
 
* 3 metal layers
−
* 1,680,000 transistors
+
* 1,681,999 transistors
−
* 13.9 mm x 16.8 mm
+
* 13.8684 mm x 16.764 mm
−
* 233.52 mm² die size
+
* 232.49 mm² die size
 
* PGA-431
 
* PGA-431
 
** 291 signal pins
 
** 291 signal pins

Latest revision as of 01:09, 4 August 2017

Edit Values
Alpha 21064 µarch
General Info
Arch TypeCPU
DesignerDEC
ManufacturerDEC
IntroductionNovember 20, 1992
Process0.75 µm, 0.675 µm
Core Configs1
Pipeline
TypeSuperscalar
OoOENo
SpeculativeYes
Reg RenamingNo
Stages7-12
Decode2-way
Instructions
ISAAlpha
Cache
L1I Cache8 KiB/core
direct-mapped
L1D Cache8 KiB/core
direct-mapped
L2 Cache0.125-16 MiB/motherboard
Succession

Alpha 21064 was the first Alpha microarchitecture designed by DEC and introduced in 1992.

Etymology[edit]

The microarchitecture name Alpha 21064 is composed of both the ISA and the implementation. In particular, the "Alpha" refers to DEC's Alpha AXP instruction set architecture while the "21064" refers to a "21st century"-ready 64-bit "generation 0" microarchitecture.

Initial test chips were called EV-3 (Extended VAX on CMOS-3) whereas the final chips were called EV-4 (Extended VAX on CMOS-4).

Release Dates[edit]

Tape-out for the Alpha 21064 occurred on July 14, 1991. First parts were available on August 30 and a successful boot-up took place on November 3 the same year. DEC first announced their 21064 architecture in February of 1992. Alpha 21064-based chips were first introduced during COMDEX on November 20, 1992.

Process Technology[edit]

See also: 0.75 µm process

Alpha 21064 was manufactured on DEC's CMOS-4, their then-newest 0.75 µm process. The process offered three levels of aluminum interconnects and a nominal 3.3 V power supply. Note that prior to the introduction of the 21064, DEC produced early "assistance" samples for software developers which were manufactured on an older CMOS-3 process (1 µm). For that reason those chips also had reduced cache amount, in addition to no FPU support.

Compatibility[edit]

Vendor OS Version Notes
Microsoft Windows Windows NT Support
DEC OpenVMS OpenVMS AXP V1.0 Initial OpenVMS support
DEC OSF/1 AXP 1.0
Novell Netware 3.2

Architecture[edit]

The 21064 was designed to be a very fast implementation of DEC's Alpha

  • 0.75 µm process
  • 150-200 MHz (6.6-5 ns cycles)
  • FP Unit
    • Support for IEEE 754
    • Support for VAX floating point
  • System bus
    • Separate data & address buses
    • 64/128-bit data bus
  • Directly serial ROM interface
  • Pipeline
    • 2-way instruction issue to A-/E-/F- Boxes
    • Integer Execution Unit
      • 32-entry integer register file
      • 64-bit integers operations
      • 7-stage pipeline
    • FP Execution Unit
      • 32-entry FP register file
      • 10-stage pipeline
  • Memory subsystem
    • 4-entry, 32-byte/entry write buffer

Memory Hierarchy[edit]

  • Cache
    • L1D Cache:
      • 8 KiB direct-mapped
      • 32-byte line size
      • 32-byte fill
      • write-through policy
    • L1I Cache:
      • 8 KiB direct-mapped
      • 32-byte line size
      • 32-byte fill
      • 64 ASNs
    • L2 Cache:
      • 0.125-16 MiB
      • Implemented externally on the motherboard
      • Direct on-chip pin interface
    • DRAM
      • Virtual address size
        • 64-bit, 43-bit implemented
      • Physical address size
        • 34-bit implemented

Alpha 21064 TLB consists of dedicated level one TLB for instruction cache and another one for data cache.

  • TLBs
    • ITLB
      • 8 KiB, 64 KiB, 256 KiB, 4 MiB page sizes
      • 32-entry, fully-associative
    • DTLB
      • 8 KiB page translations:
        • 8-entry, fully-associative
      • 4 MiB page translations:
        • 4-entry, fully-associative

Die[edit]

  • 30 W power dissipation @ 200 MHz, 3.3 V power supply
  • 0.75 µm process
  • 3 metal layers
  • 1,681,999 transistors
  • 13.8684 mm x 16.764 mm
  • 232.49 mm² die size
  • PGA-431
    • 291 signal pins
    • 140 power/ground rail pins

References[edit]

  • McLellan, Edward. "The Alpha AXP architecture and 21064 processor." IEEE Micro 13.3 (1993): 36-47.
Retrieved from "https://en.wikichip.org/w/index.php?title=dec/microarchitectures/alpha_21064&oldid=56784"
Facts about "Alpha 21064 - Microarchitectures - DEC"
RDF feed
codenameAlpha 21064 +
core count1 +
designerDEC +
first launchedNovember 20, 1992 +
full page namedec/microarchitectures/alpha 21064 +
instance ofmicroarchitecture +
instruction set architectureAlpha +
manufacturerDEC +
microarchitecture typeCPU +
nameAlpha 21064 +
pipeline stages (max)12 +
pipeline stages (min)7 +
process750 nm (0.75 μm, 7.5e-4 mm) + and 675 nm (0.675 μm, 6.75e-4 mm) +