From WikiChip
Difference between revisions of "dec/microarchitectures/alpha 21264"
< dec

(Created page with "{{dec title|Alpha 21264|arch}} {{microarchitecture |atype=CPU |name=Alpha 21264 |designer=DEC |manufacturer=DEC }}")
 
(→‎Process Technology)
 
(8 intermediate revisions by 2 users not shown)
Line 5: Line 5:
 
|designer=DEC
 
|designer=DEC
 
|manufacturer=DEC
 
|manufacturer=DEC
 +
|manufacturer 2=Intel
 +
|manufacturer 3=Samsung
 +
|introduction=February, 1998
 +
|process=0.35 µm
 +
|cores=1
 +
|type=Superscalar
 +
|oooe=Yes
 +
|speculative=Yes
 +
|renaming=Yes
 +
|stages=6
 +
|decode=4-way
 +
|isa=Alpha
 +
|l1i=64 KiB
 +
|l1i per=core
 +
|l1i desc=2-way set associative
 +
|l1d=64 KiB
 +
|l1d per=core
 +
|l1d desc=2-way set associative
 +
|predecessor=Alpha 21164
 +
|predecessor link=dec/microarchitectures/alpha_21164
 +
|successor=Alpha 21364
 +
|successor link=compaq/microarchitectures/alpha_21364
 
}}
 
}}
 +
'''Alpha 21264''' was an [[Alpha]] microarchitecture designed by [[DEC]] and introduced in 1998 by [[Compaq]] as a successor to the {{\\|Alpha 21164}} architecture.
 +
 +
== History ==
 +
{{empty section}}
 +
 +
== Process Technology ==
 +
{{see also|0.35 µm process}}
 +
Alpha 21264 was manufactured on a [[0.35 µm process]] at DEC's own Hudson foundry. The process had a 0.35 µm drawn gate length and 0.25 µm effective channel length. The CMOS process had 3 metal layers. The chip allowed for a supply voltage of up to 2 V in order to limit the chips to a power limit of 72 W, although it was actually designed to reliably operate at up to 2.5 V.
 +
 +
== Architecture ==
 +
{{empty section}}
 +
* Integrated PLL (designed by [[Swiss Center for Electronics and Microtechnology|CSEM]])
 +
== Die ==
 +
* 15,200,000 transistors
 +
** 9,200,000 cache
 +
** 6,000,000 logic
 +
* [[0.35 µm]] 4 metal layers
 +
* 16.7 mm x 18.8 mm
 +
* 313.96 mm² die size
 +
* PGA-587 package
 +
** 389 signal pins
 +
 +
 +
: [[File:alpha 21264 die shot.png|650px]]
 +
 +
 +
: [[File:alpha 21264 die shot (annotated).png|650px]]
 +
 +
== All Alpha 21264 chips ==
 +
{{empty section}}
 +
 +
== References ==
 +
* Dobberpuhl, Daniel W. "Circuits and technology for Digital's StrongARM and ALPHA microprocessors [CMOS technology]." Advanced Research in VLSI, 1997. Proceedings., Seventeenth Conference on. IEEE, 1997.

Latest revision as of 05:59, 13 June 2017

Edit Values
Alpha 21264 µarch
General Info
Arch TypeCPU
DesignerDEC
ManufacturerDEC, Intel, Samsung
IntroductionFebruary, 1998
Process0.35 µm
Core Configs1
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages6
Decode4-way
Instructions
ISAAlpha
Cache
L1I Cache64 KiB/core
2-way set associative
L1D Cache64 KiB/core
2-way set associative
Succession

Alpha 21264 was an Alpha microarchitecture designed by DEC and introduced in 1998 by Compaq as a successor to the Alpha 21164 architecture.

History[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Process Technology[edit]

See also: 0.35 µm process

Alpha 21264 was manufactured on a 0.35 µm process at DEC's own Hudson foundry. The process had a 0.35 µm drawn gate length and 0.25 µm effective channel length. The CMOS process had 3 metal layers. The chip allowed for a supply voltage of up to 2 V in order to limit the chips to a power limit of 72 W, although it was actually designed to reliably operate at up to 2.5 V.

Architecture[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.
  • Integrated PLL (designed by CSEM)

Die[edit]

  • 15,200,000 transistors
    • 9,200,000 cache
    • 6,000,000 logic
  • 0.35 µm 4 metal layers
  • 16.7 mm x 18.8 mm
  • 313.96 mm² die size
  • PGA-587 package
    • 389 signal pins


alpha 21264 die shot.png


alpha 21264 die shot (annotated).png

All Alpha 21264 chips[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

References[edit]

  • Dobberpuhl, Daniel W. "Circuits and technology for Digital's StrongARM and ALPHA microprocessors [CMOS technology]." Advanced Research in VLSI, 1997. Proceedings., Seventeenth Conference on. IEEE, 1997.
Retrieved from "https://en.wikichip.org/w/index.php?title=dec/microarchitectures/alpha_21264&oldid=44606"
Facts about "Alpha 21264 - Microarchitectures - DEC"
RDF feed
codenameAlpha 21264 +
core count1 +
designerDEC +
first launchedFebruary 1998 +
full page namedec/microarchitectures/alpha 21264 +
instance ofmicroarchitecture +
instruction set architectureAlpha +
manufacturerDEC + and Intel +
microarchitecture typeCPU +
nameAlpha 21264 +
pipeline stages6 +
process350 nm (0.35 μm, 3.5e-4 mm) +