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Difference between revisions of "intel/xeon gold/5117"
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{{intel title|Xeon Gold 5117}}
 
{{intel title|Xeon Gold 5117}}
−
{{mpu
+
{{chip
−
| future              = Yes
+
|name=Xeon Gold 5117
−
| name               = Xeon Gold 5117
+
|image=skylake sp (basic).png
−
| no image           = Yes
+
|designer=Intel
−
| image              =
+
|manufacturer=Intel
−
| image size          =
+
|model number=5117
−
| caption            =  
+
|s-spec=SR37S
−
| designer           = Intel
+
|s-spec qs=QM8S
−
| manufacturer       = Intel
+
|market=Server
−
| model number       = 5117
+
|first announced=July 11, 2017
−
| part number        =
+
|first launched=July 11, 2017
−
| part number 1      =
+
|family=Xeon Gold
−
| part number 2      =
+
|series=5100
−
| s-spec             =  
+
|locked=Yes
−
| s-spec 2            =  
+
|frequency=2,000 MHz
−
| market             = Server
+
|turbo frequency1=2,800 MHz
−
| first announced     = April 25, 2017
+
|clock multiplier=20
−
| first launched     =
+
|cpuid=0x50654
−
| last order          =
+
|isa=x86-64
−
| last shipment      =
+
|isa family=x86
−
| release price      =  
+
|microarch=Skylake (server)
−
 
+
|platform=Purley
−
| family             = Xeon Gold
+
|chipset=Lewisburg
−
| series             = 5000
+
|core name=Skylake SP
−
| locked             = Yes
+
|core family=6
−
| frequency           = 2.0 GHz
+
|process=14 nm
−
| turbo frequency    =
+
|technology=CMOS
−
| turbo frequency1   =
+
|word size=64 bit
−
| turbo frequency2    =  
+
|core count=14
−
| turbo frequency3    =
+
|thread count=28
−
| turbo frequency4    =
+
|max cpus=4
−
| turbo frequency5    =
+
|max memory=768 GiB
−
| turbo frequency6    =
+
|tdp=105 W
−
| turbo frequency7    =
+
|tcase min=0 °C
−
| turbo frequency8    =
+
|tcase max=81 °C
−
| bus type            = DMI 3.0
+
|package name 1=intel,fclga_3647
−
| bus speed          =
+
|successor=Xeon Gold 5217
−
| bus rate            = 8 GT/s
+
|successor link=intel/xeon_gold/5217
−
| bus links          = 4
 
−
| clock multiplier   = 20
 
−
| cpuid               =  
 
−
| cpuid 2            =
 
−
 
 
−
| isa family          = x86-64
 
−
| isa                 = x86
 
−
| microarch           = Skylake
 
−
| platform           = Purley
 
−
| chipset             = Lewisburg
 
−
| core name           = Skylake SP
 
−
| core family         =  
 
−
| core model          =
 
−
| core stepping      = H0
 
−
| process             = 14 nm
 
−
| transistors        =
 
−
| technology         = CMOS
 
−
| die area            = <!-- XX mm² -->
 
−
| die width          =
 
−
| die length          =
 
−
| word size           = 64 bit
 
−
| core count         = 28
 
−
| thread count       = 56
 
−
| max cpus           = 2
 
−
| max memory         =
 
−
 
 
−
| electrical          =
 
−
| power              =
 
−
| average power      =
 
−
| idle power          =
 
−
| v core              =
 
−
| v core tolerance    = <!-- OR ... -->
 
−
| v core min          =
 
−
| v core max          =
 
−
| v io                =
 
−
| v io tolerance      =
 
−
| v io 2              = <!-- OR ... -->
 
−
| v io 3              =
 
−
| sdp                =  
 
−
| tdp                 =  
 
−
| tdp typical        =
 
−
| ctdp down          =
 
−
| ctdp down frequency =
 
−
| ctdp up            =
 
−
| ctdp up frequency  =
 
−
| temp min           = <!-- use TJ/TC whenever possible instead -->
 
−
| temp max            =
 
−
| tjunc min          = <!-- .. °C -->
 
−
| tjunc max          =
 
−
| tcase min          =
 
−
| tcase max           =
 
−
| tstorage min        =
 
−
| tstorage max        =
 
−
| tambient min        =  
 
−
| tambient max        =
 
−
 
 
−
| package module 1   =
 
−
| package module 2    =  
 
−
<!-------- USE ONLY IF MUST, OTHERWISE TRY TO USE MODULE ABOVE -------------->
 
−
| packaging          = Yes
 
−
| package 0          = FCLGA-3647
 
−
| package 0 type      = LGA
 
−
| package 0 pins      = 3647
 
−
| package 0 pitch    =
 
−
| package 0 width    =
 
−
| package 0 length    =
 
−
| package 0 height    =
 
−
| socket 0            = LGA-3647
 
−
| socket 0 type      = LGA
 
 
}}
 
}}
−
'''Xeon Gold 5117''' is a {{arch|64}} [[x86]] high-performance server [[octacosa-core]] [[multiprocessor]] set to be introduced by [[Intel]] in the second quarter of 2017. This processor is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture (a {{intel|Skylake SP|l=core}} core) and is manufactured on Intel's [[14 nm process]]. The 5117 operates at 2 GHz.
+
'''Xeon Gold 5117''' is a {{arch|64}} [[tetradeca-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 5117, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 1 {{x86|AVX-512}} [[FMA]] unit as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2 GHz with a TDP of 105 W and a {{intel|turbo boost}} frequency of up to 2.8 GHz, supports up 768 GiB of hexa-channel DDR4-2400 ECC memory.
−
 
 
−
 
 
−
{{unknown features}}
 
  
 
== Cache ==
 
== Cache ==
−
{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
+
{{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}}
 
{{cache size
 
{{cache size
−
|l1 cache=1.75 MiB
+
|l1 cache=896 KiB
−
|l1i cache=896 KiB
+
|l1i cache=448 KiB
−
|l1i break=28x32 KiB
+
|l1i break=14x32 KiB
 
|l1i desc=8-way set associative
 
|l1i desc=8-way set associative
−
|l1d cache=896 KiB
+
|l1d cache=448 KiB
−
|l1d break=28x32 KiB
+
|l1d break=14x32 KiB
 
|l1d desc=8-way set associative
 
|l1d desc=8-way set associative
 
|l1d policy=write-back
 
|l1d policy=write-back
−
|l2 cache=28 MiB
+
|l2 cache=14 MiB
−
|l2 break=28x1 MiB
+
|l2 break=14x1 MiB
 
|l2 desc=16-way set associative
 
|l2 desc=16-way set associative
 
|l2 policy=write-back
 
|l2 policy=write-back
−
|l3 cache=38.5 MiB
+
|l3 cache=19.25 MiB
−
|l3 break=28x1.375 MiB
+
|l3 break=14x1.375 MiB
 
|l3 desc=11-way set associative
 
|l3 desc=11-way set associative
 
|l3 policy=write-back
 
|l3 policy=write-back
Line 136: Line 64:
 
== Memory controller ==
 
== Memory controller ==
 
{{memory controller
 
{{memory controller
−
|type=DDR4-2666
+
|type=DDR4-2400
 
|ecc=Yes
 
|ecc=Yes
−
|max mem=
+
|max mem=768 GiB
−
|controllers=1
+
|controllers=2
 
|channels=6
 
|channels=6
−
|max bandwidth=119.21 GiB/s
+
|max bandwidth=107.3 GiB/s
−
|bandwidth schan=19.89 GiB/s
+
|bandwidth schan=17.88 GiB/s
−
|bandwidth dchan=39.72 GiB/s
+
|bandwidth dchan=35.76 GiB/s
−
|bandwidth qchan=79.47 GiB/s
+
|bandwidth qchan=71.53 GiB/s
−
|bandwidth hchan=119.21 GiB/s
+
|bandwidth hchan=107.3 GiB/s
 
}}
 
}}
 +
 +
== Expansions ==
 +
{{expansions
 +
| pcie revision      = 3.0
 +
| pcie lanes        = 48
 +
| pcie config        = x16
 +
| pcie config 2      = x8
 +
| pcie config 3      = x4
 +
}}
 +
 +
== Features ==
 +
{{x86 features
 +
|real=Yes
 +
|protected=Yes
 +
|smm=Yes
 +
|fpu=Yes
 +
|x8616=Yes
 +
|x8632=Yes
 +
|x8664=Yes
 +
|nx=Yes
 +
|mmx=Yes
 +
|emmx=Yes
 +
|sse=Yes
 +
|sse2=Yes
 +
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=Yes
 +
|sse42=Yes
 +
|sse4a=No
 +
|avx=Yes
 +
|avx2=Yes
 +
|avx512f=Yes
 +
|avx512cd=Yes
 +
|avx512er=No
 +
|avx512pf=No
 +
|avx512bw=Yes
 +
|avx512dq=Yes
 +
|avx512vl=Yes
 +
|avx512ifma=No
 +
|avx512vbmi=No
 +
|avx5124fmaps=No
 +
|avx5124vnniw=No
 +
|avx512vpopcntdq=No
 +
|abm=Yes
 +
|tbm=No
 +
|bmi1=Yes
 +
|bmi2=Yes
 +
|fma3=Yes
 +
|fma4=No
 +
|aes=Yes
 +
|rdrand=Yes
 +
|sha=No
 +
|xop=No
 +
|adx=Yes
 +
|clmul=Yes
 +
|f16c=Yes
 +
|tbt1=No
 +
|tbt2=Yes
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=Yes
 +
|sst=Yes
 +
|flex=No
 +
|fastmem=No
 +
|ivmd=Yes
 +
|intelnode=Yes
 +
|kpt=Yes
 +
|ptt=Yes
 +
|mbe=Yes
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=Yes
 +
|txt=Yes
 +
|ht=Yes
 +
|vpro=Yes
 +
|vtx=Yes
 +
|vtd=No
 +
|ept=Yes
 +
|mpx=No
 +
|sgx=No
 +
|securekey=No
 +
|osguard=No
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 +
}}
 +
 +
== Frequencies ==
 +
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
 +
{{frequency table
 +
|freq_base=2,000 MHz
 +
|freq_1=2,800 MHz
 +
|freq_2=2,800 MHz
 +
|freq_3=2,600 MHz
 +
|freq_4=2,600 MHz
 +
|freq_5=2,500 MHz
 +
|freq_6=2,500 MHz
 +
|freq_7=2,500 MHz
 +
|freq_8=2,500 MHz
 +
|freq_9=2,400 MHz
 +
|freq_10=2,400 MHz
 +
|freq_11=2,400 MHz
 +
|freq_12=2,400 MHz
 +
|freq_13=2,300 MHz
 +
|freq_14=2,300 MHz
 +
|freq_avx2_base=1,300 MHz
 +
|freq_avx2_1=2,800 MHz
 +
|freq_avx2_2=2,800 MHz
 +
|freq_avx2_3=2,500 MHz
 +
|freq_avx2_4=2,500 MHz
 +
|freq_avx2_5=1,900 MHz
 +
|freq_avx2_6=1,900 MHz
 +
|freq_avx2_7=1,900 MHz
 +
|freq_avx2_8=1,900 MHz
 +
|freq_avx2_9=1,600 MHz
 +
|freq_avx2_10=1,600 MHz
 +
|freq_avx2_11=1,600 MHz
 +
|freq_avx2_12=1,600 MHz
 +
|freq_avx2_13=1,600 MHz
 +
|freq_avx2_14=1,600 MHz
 +
|freq_avx512_base=1,100 MHz
 +
|freq_avx512_1=2,800 MHz
 +
|freq_avx512_2=2,800 MHz
 +
|freq_avx512_3=2,200 MHz
 +
|freq_avx512_4=2,200 MHz
 +
|freq_avx512_5=1,700 MHz
 +
|freq_avx512_6=1,700 MHz
 +
|freq_avx512_7=1,700 MHz
 +
|freq_avx512_8=1,700 MHz
 +
|freq_avx512_9=1,400 MHz
 +
|freq_avx512_10=1,400 MHz
 +
|freq_avx512_11=1,400 MHz
 +
|freq_avx512_12=1,400 MHz
 +
|freq_avx512_13=1,400 MHz
 +
|freq_avx512_14=1,400 MHz
 +
}}
 +
 +
[[Category:microprocessor models by intel based on skylake extreme core count die]]

Latest revision as of 19:13, 3 August 2022

Edit Values
Xeon Gold 5117
skylake sp (basic).png
General Info
DesignerIntel
ManufacturerIntel
Model Number5117
S-SpecSR37S
QM8S (QS)
MarketServer
IntroductionJuly 11, 2017 (announced)
July 11, 2017 (launched)
ShopAmazon
General Specs
FamilyXeon Gold
Series5100
LockedYes
Frequency2,000 MHz
Turbo Frequency2,800 MHz (1 core)
Clock multiplier20
CPUID0x50654
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureSkylake (server)
PlatformPurley
ChipsetLewisburg
Core NameSkylake SP
Core Family6
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores14
Threads28
Max Memory768 GiB
Multiprocessing
Max SMP4-Way (Multiprocessor)
Electrical
TDP105 W
Tcase0 °C – 81 °C
Packaging
PackageFCLGA-3647 (FCLGA)
Dimension76.16 mm × 56.6 mm
Pitch0.8585 mm × 0.9906 mm
Contacts3647
SocketSocket P, LGA-3647
Succession

Xeon Gold 5117 is a 64-bit tetradeca-core x86 multi-socket high performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 5117, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 1 AVX-512 FMA unit as well as three Ultra Path Interconnect links. This microprocessor, which operates at 2 GHz with a TDP of 105 W and a turbo boost frequency of up to 2.8 GHz, supports up 768 GiB of hexa-channel DDR4-2400 ECC memory.

Cache[edit]

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$896 KiB
917,504 B
0.875 MiB
L1I$448 KiB
458,752 B
0.438 MiB
14x32 KiB8-way set associative 
L1D$448 KiB
458,752 B
0.438 MiB
14x32 KiB8-way set associativewrite-back
L2$14 MiB
14,336 KiB
14,680,064 B
0.0137 GiB
  14x1 MiB16-way set associativewrite-back
L3$19.25 MiB
19,712 KiB
20,185,088 B
0.0188 GiB
  14x1.375 MiB11-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2400
Supports ECCYes
Max Mem768 GiB
Controllers2
Channels6
Max Bandwidth107.3 GiB/s
109,875.2 MiB/s
115.212 GB/s
115,212.498 MB/s
0.105 TiB/s
0.115 TB/s
Bandwidth
Single 17.88 GiB/s
Double 35.76 GiB/s
Quad 71.53 GiB/s
Hexa 107.3 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes48
Configsx16, x8, x4


Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
VMDVolume Management Device
NMNode Manager
KPTKey Protection Technology
PTTPlatform Trust Technology
MBE CtrlMode-Based Execute Control

Frequencies[edit]

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

ModeBaseTurbo Frequency/Active Cores
1234567891011121314
Normal2,000 MHz2,800 MHz2,800 MHz2,600 MHz2,600 MHz2,500 MHz2,500 MHz2,500 MHz2,500 MHz2,400 MHz2,400 MHz2,400 MHz2,400 MHz2,300 MHz2,300 MHz
AVX21,300 MHz2,800 MHz2,800 MHz2,500 MHz2,500 MHz1,900 MHz1,900 MHz1,900 MHz1,900 MHz1,600 MHz1,600 MHz1,600 MHz1,600 MHz1,600 MHz1,600 MHz
AVX5121,100 MHz2,800 MHz2,800 MHz2,200 MHz2,200 MHz1,700 MHz1,700 MHz1,700 MHz1,700 MHz1,400 MHz1,400 MHz1,400 MHz1,400 MHz1,400 MHz1,400 MHz
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_gold/5117&oldid=100359"
Facts about "Xeon Gold 5117 - Intel"
RDF feed
has ecc memory supporttrue +
l1$ size1,792 KiB (1,835,008 B, 1.75 MiB) +
l1d$ description8-way set associative +
l1d$ size896 KiB (917,504 B, 0.875 MiB) +
l1i$ description8-way set associative +
l1i$ size896 KiB (917,504 B, 0.875 MiB) +
l2$ description16-way set associative +
l2$ size28 MiB (28,672 KiB, 29,360,128 B, 0.0273 GiB) +
l3$ description16-way set associative +
l3$ size38.5 MiB (39,424 KiB, 40,370,176 B, 0.0376 GiB) +
max memory bandwidth119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels6 +
supported memory typeDDR4-2666 +