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<div id="wc_menu_export"></div>@@_START_A_BUTTON_@@<i class="fa fa-company-intel" aria-hidden="true"></i><span class="mob-collapse">&nbsp;Intel&nbsp;<i class="fa fa-angle-down" aria-hidden="true"></i></span>@@_END_A_BUTTON_@@<div style="padding: 20px;" class="collapse">
 +
<div><span style="font-size: 1.2em; margin: 10px; display: block;">Popular Families</span><hr style="display: block; height: 1px; border: 0; border-top: 1px solid #b7b7b7; margin: 1em 0; padding: 0;"><div style="display: flex;"><ul class="items"><li>@@_START_H5_@@Intel@@_END_H5_@@<ul style="list-style:none; display: flex; flex-direction: column;"><li>Core i3</li></ul></li></ul></div></div>
 +
<div><span style="font-size: 1.2em; margin: 10px; display: block;">Popular Families</span><hr style="display: block; height: 1px; border: 0; border-top: 1px solid #b7b7b7; margin: 1em 0; padding: 0;"><div style="display: flex;"><ul class="items"><li>@@_START_H5_@@Intel@@_END_H5_@@<ul style="list-style:none; display: flex; flex-direction: column;"><li>Core i3</li></ul></li></ul></div></div>
 +
<div><span style="font-size: 1.2em; margin: 10px; display: block;">Popular Families</span><hr style="display: block; height: 1px; border: 0; border-top: 1px solid #b7b7b7; margin: 1em 0; padding: 0;"><div style="display: flex;"><ul class="items"><li>@@_START_H5_@@Intel@@_END_H5_@@<ul style="list-style:none; display: flex; flex-direction: column;"><li>Core i3</li></ul></li></ul></div></div>
 +
</div><div id="wc_menu_export"></div>
 
Welcome to this sandbox page. Sandbox pages provide space to experiment with the process of editing.
 
Welcome to this sandbox page. Sandbox pages provide space to experiment with the process of editing.
 
<hr />
 
<hr />
  
 +
=== <span style="float: right;">header text right</span> ===
  
 +
== test ==
 
<table style="border: 1px solid black; border-collapse: collapse; border-spacing:0; text-align: center;">
 
<table style="border: 1px solid black; border-collapse: collapse; border-spacing:0; text-align: center;">
 
<tr><td colspan="9">ssssssssssss</td></tr>
 
<tr><td colspan="9">ssssssssssss</td></tr>
Line 89: Line 96:
  
 
== comptable ==
 
== comptable ==
 +
{{#invoke: arch timeline|intel_x86}}
 +
 +
{{#time:09/01/2015}}
 +
 
<timeline>
 
<timeline>
−
ImageSize  = width:1000 height:300
+
ImageSize  = width:1000 height:500
−
PlotArea  = left:20 right:10 top:10 bottom:25 #left:0 right:0 bottom:20 top:0
+
PlotArea  = left:150 right:10 top:10 bottom:25 #left:0 right:0 bottom:20 top:0
  
 
DateFormat = mm/dd/yyyy
 
DateFormat = mm/dd/yyyy
Line 114: Line 125:
 
   id:c_core1 value:rgb(0.47,0.83,0.91)
 
   id:c_core1 value:rgb(0.47,0.83,0.91)
 
   id:c_core2 value:rgb(0.97,0.90,0.72)
 
   id:c_core2 value:rgb(0.97,0.90,0.72)
−
   id:c_core3 value:rgb(0.98,0.73,0.87)
+
   id:c_core3 value:rgb(0.68,1,0.91)
−
   id:c_core4 value:rgb(0.78,0.82,0.96)
+
   id:c_core4 value:rgb(0.98,0.73,0.87)
−
   id:c_core5 value:rgb(0.84,0.97,0.96)
+
   id:c_core5 value:rgb(0.78,0.82,0.96)
−
   id:c_core6 value:rgb(0.95,0.83,1)
+
   id:c_core6 value:rgb(0.84,0.97,0.96)
−
   id:c_core7 value:rgb(0.89,0.95,0.87)
+
   id:c_core7 value:rgb(0.95,0.83,1)
−
   id:c_core8 value:rgb(0.68,1,0.91)
+
   id:c_core8 value:rgb(0.89,0.95,0.87)
 
   id:c_core9 value:rgb(0.78,0.93,1)
 
   id:c_core9 value:rgb(0.78,0.93,1)
  
Line 133: Line 144:
 
     bar:arch8
 
     bar:arch8
 
     bar:arch9
 
     bar:arch9
−
   barset:Cores
+
   barset:Cores1
−
     bar:core1
+
     bar:core11
−
     bar:core2
+
     bar:core12
−
     bar:core3
+
     bar:core13
−
     bar:core4
+
     bar:core14
−
     bar:core5
+
     bar:core15
−
     bar:core6
+
     bar:core16
−
     bar:core7
+
  barset:Cores2
−
     bar:core8
+
    bar:core21
−
     bar:core9
+
    bar:core22
 +
    bar:core23
 +
    bar:core24
 +
    bar:core25
 +
    bar:core26
 +
  barset:Cores3
 +
    bar:core31
 +
    bar:core32
 +
    bar:core33
 +
    bar:core34
 +
    bar:core35
 +
    bar:core36
 +
  barset:Cores4
 +
    bar:core41
 +
    bar:core42
 +
    bar:core43
 +
    bar:core44
 +
    bar:core45
 +
    bar:core46
 +
  barset:Cores5
 +
    bar:core51
 +
    bar:core52
 +
    bar:core53
 +
    bar:core54
 +
    bar:core55
 +
    bar:core56
 +
  barset:Cores6
 +
    bar:core61
 +
    bar:core62
 +
    bar:core63
 +
    bar:core64
 +
    bar:core65
 +
    bar:core66
 +
  barset:Cores7
 +
    bar:core71
 +
    bar:core72
 +
    bar:core73
 +
    bar:core74
 +
    bar:core75
 +
    bar:core76
 +
  barset:Cores8
 +
    bar:core81
 +
    bar:core82
 +
    bar:core83
 +
    bar:core84
 +
    bar:core85
 +
    bar:core86
 +
  barset:Cores9
 +
    bar:core91
 +
    bar:core92
 +
    bar:core93
 +
     bar:core94
 +
     bar:core95
 +
     bar:core96
 
PlotData=
 
PlotData=
 
   width:22 fontsize:10 textcolor:black shift:(5,-4)
 
   width:22 fontsize:10 textcolor:black shift:(5,-4)
Line 152: Line 216:
 
   bar:arch6 color:c_arch6 from:08/01/2019 till:01/01/2021 anchor:from text:"[[intel/microarchitectures/tigerlake|Tigerlake]]"
 
   bar:arch6 color:c_arch6 from:08/01/2019 till:01/01/2021 anchor:from text:"[[intel/microarchitectures/tigerlake|Tigerlake]]"
  
−
   width:15 fontsize:10
+
   width:10 fontsize:10
 
   color:c_core1  
 
   color:c_core1  
−
   bar:core1
+
   bar:core11 anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake Y"
−
    anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake Y"
+
  bar:core12 anchor:from from:11/20/2016 till:11/09/2017 text:"Kaby Lake Y"
−
    anchor:from from:11/20/2016 till:11/09/2017 text:"Kaby Lake Y"
+
  bar:core13 anchor:from from:11/12/2017 till:02/09/2019 text:"Cannonlake Y"
−
    anchor:from from:11/12/2017 till:02/09/2019 text:"Cannonlake Y"
 
 
   color:c_core2
 
   color:c_core2
−
   bar:core2
+
   bar:core21 anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake U"
−
    anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake Y2"
+
  bar:core22 anchor:from from:11/20/2016 till:11/09/2017 text:"Kaby Lake U"
−
    anchor:from from:11/20/2016 till:11/09/2017 text:"Skylake U2"
+
  bar:core23 anchor:from from:11/12/2017 till:02/09/2019 text:"Cannonlake U"
 
   color:c_core3
 
   color:c_core3
−
   bar:core3
+
   bar:core31 anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake H"
−
    anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake Y3"
+
  bar:core32 anchor:from from:11/20/2016 till:11/09/2017 text:"Kaby Lake H"
−
    anchor:from from:11/20/2016 till:11/09/2017 text:"Skylake U3"
+
  bar:core33 anchor:from from:11/12/2017 till:02/09/2019 text:"Cannonlake H"
 
   color:c_core4
 
   color:c_core4
−
   bar:core4
+
   bar:core41 anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake S"
−
    anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake Y4"
+
  bar:core42 anchor:from from:11/20/2016 till:11/09/2017 text:"Kaby Lake S"
−
    anchor:from from:11/20/2016 till:11/09/2017 text:"Skylake U4"
+
  bar:core43 anchor:from from:11/12/2017 till:02/09/2019 text:"Cannonlake S"
 
   color:c_core5
 
   color:c_core5
−
   bar:core5
+
   bar:core51 anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake DT"
−
    anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake Y5"
+
  bar:core52 anchor:from from:11/20/2016 till:11/09/2017 text:"Kaby Lake DT"
−
    anchor:from from:11/20/2016 till:11/09/2017 text:"Skylake U5"
+
  bar:core53 anchor:from from:11/12/2017 till:02/09/2019 text:"Cannonlake DT"
 
   color:c_core6
 
   color:c_core6
−
   bar:core6
+
   bar:core61 anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake X"
−
    anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake Y6"
+
  bar:core62 anchor:from from:11/20/2016 till:11/09/2017 text:"Kaby Lake X"
−
    anchor:from from:11/20/2016 till:11/09/2017 text:"Skylake U6"
+
  bar:core63 anchor:from from:11/12/2017 till:02/09/2019 text:"Cannonlake X"
 
   color:c_core7
 
   color:c_core7
−
   bar:core7
+
   bar:core71 anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake E"
−
    anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake Y7"
+
  bar:core72 anchor:from from:11/20/2016 till:11/09/2017 text:"Kaby Lake E"
−
    anchor:from from:11/20/2016 till:11/09/2017 text:"Skylake U7"
+
  bar:core73 anchor:from from:11/12/2017 till:02/09/2019 text:"Cannonlake E"
 
   color:c_core8
 
   color:c_core8
−
   bar:core8
+
   bar:core81 anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake EP"
−
    anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake Y8"
+
  bar:core82 anchor:from from:11/20/2016 till:11/09/2017 text:"Kaby Lake EP"
−
    anchor:from from:11/20/2016 till:11/09/2017 text:"Skylake U8"
+
  bar:core83 anchor:from from:11/12/2017 till:02/09/2019 text:"Cannonlake EP"
 
   color:c_core9
 
   color:c_core9
−
   bar:core9
+
   bar:core91 anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake EX"
−
    anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake Y9"
+
  bar:core92 anchor:from from:11/20/2016 till:11/09/2017 text:"Kaby Lake EX"
−
    anchor:from from:11/20/2016 till:11/09/2017 text:"Skylake U9"
+
  bar:core93 anchor:from from:11/12/2017 till:02/09/2019 text:"Cannonlake EX"
 
</timeline>
 
</timeline>
  

Latest revision as of 21:32, 7 February 2020

Welcome to this sandbox page. Sandbox pages provide space to experiment with the process of editing.

header text right[edit]

test[edit]

 
ssssssssssss
DATA
BUS
I/O		D00116CM-RAM0X
D10215CM-RAM1X
D20314CM-RAM2X
 D30413CM-RAM3X
Vss0512VddX
CLOCK
PHASE 1/2		Ø10611CM-ROMX
Ø20710TESTX
SYNC0809RESETX
123456789


Sitemap font awesome.svgCache Info
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes.
[Edit Values]
L1$128 KiB
L1I$64 KiB1x64 KiB2-way set associativewrite-back
L1D$64 KiB1x64 KiB2-way set associativewrite-back
L2$128 KiB
L2I$64 KiB1x64 KiB2-way set associativewrite-back
L2D$64 KiB1x64 KiB2-way set associativewrite-back
L3$128 KiB
L3I$64 KiB1x64 KiB2-way set associativewrite-back
L3D$64 KiB1x64 KiB2-way set associativewrite-back
L4$128 KiB
L4I$64 KiB1x64 KiB2-way set associativewrite-back
L4D$64 KiB1x64 KiB2-way set associativewrite-back
Off-package cache support
Mobo512 KiB
1x64 KiB2-way set associativewrite-back


wireless test[edit]

Antu network-wireless-connected-100.svgWireless Communications
Wi-Fi
WiFi
802.11-1997Yes
802.11aYes
802.11bYes
802.11gYes
802.11nYes
802.11acYes
802.11adYes
Cellular
2G
GSM Yes
GPRS Yes
EDGE Yes
cdmaOne
IS-95AYes
IS-95BYes
3G
UMTS
WCDMAYes
HSDPAYes7.2 Mbps
HSUPAYes5.76 Mbps
CDMA2000
1XYes
1xEV-DOYes
1X AdvancedYes
Satellite

mpu[edit]

AMD-X5-133ADW
KL AMD 5x86.jpg
General Info
DesignerAMD
ManufacturerAMD
Model NumberAMD-X5-133ADW
Part NumberAMD-X5-133ADW,
AMD-X5-133ADW,
AMD-X5-133ADW
MarketDesktop
MarketDesktop
ecd9c6

comptable[edit]

Script error: The function "intel_x86" does not exist.

09/01/2015

intel/microarchitectures/tigerlakeintel/microarchitectures/icelakeintel/microarchitectures/cannonlakeintel/microarchitectures/coffee lakeintel/microarchitectures/kaby lakeintel/microarchitectures/skylake


Tabl test[edit]

Microarchitecture template[edit]

Microarchitectures
Paradigms
Single-CycleMulti-CyclePipelining
SuperpipeliningSuperscalarOOoE
Pipeline
Prefetching (instruction prefetch)
Fetching (instruction fetch)
Decoding (instruction decode)
micro-operationmacro-operationinternal operation
µOP cacheµOP fusion 
Out-of-Order
OOoESpeculativeFlushing
Components
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