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{{intel title|Atom Z520}} | {{intel title|Atom Z520}} | ||
− | {{ | + | {{chip |
| name = Atom Z520 | | name = Atom Z520 | ||
| no image = | | no image = | ||
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| model number = Z520 | | model number = Z520 | ||
| part number = AC80566UE014DW | | part number = AC80566UE014DW | ||
− | | part number | + | | part number 2 = |
| s-spec = SLB2H | | s-spec = SLB2H | ||
| s-spec 2 = | | s-spec 2 = | ||
− | | s-spec qs = | + | | s-spec qs = QEQS |
| market = Mobile | | market = Mobile | ||
| first announced = April 2, 2008 | | first announced = April 2, 2008 | ||
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| last order = | | last order = | ||
| last shipment = | | last shipment = | ||
− | | release price = | + | | release price = $65 |
| family = Atom | | family = Atom | ||
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| max cpus = 1 | | max cpus = 1 | ||
− | + | ||
| power = | | power = | ||
| average power = 220 mW | | average power = 220 mW | ||
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'''Z520''' is an ultra-low power {{arch|32}} [[x86]] microprocessor introduced by [[Intel]] in early 2008 specifically for Mobile Internet Devices (MID). The Z520, which is based on the {{intel|Bonnell|l=arch}} microarchitecture ({{intel|Silverthorne|l=core}} core), is manufactured on a [[45 nm process]]. This processor operates at 1.33 Ghz with a TDP of just 2 W and an average power of 220 mW. The MPU features a legacy 533 MT/s [[front-side bus]] capable of communicating with the {{intel|Poulsbo|l=chipset}} chipset in both low-power [[CMOS]] mode as well as normal [[GTL]] mode (which also works with other chipsets). | '''Z520''' is an ultra-low power {{arch|32}} [[x86]] microprocessor introduced by [[Intel]] in early 2008 specifically for Mobile Internet Devices (MID). The Z520, which is based on the {{intel|Bonnell|l=arch}} microarchitecture ({{intel|Silverthorne|l=core}} core), is manufactured on a [[45 nm process]]. This processor operates at 1.33 Ghz with a TDP of just 2 W and an average power of 220 mW. The MPU features a legacy 533 MT/s [[front-side bus]] capable of communicating with the {{intel|Poulsbo|l=chipset}} chipset in both low-power [[CMOS]] mode as well as normal [[GTL]] mode (which also works with other chipsets). | ||
− | This processor has a TDP of 2 W when {{intel|Hyper-Threading}} is disabled and 2.2 W when enabled. | + | This processor has a TDP of 2 W when {{intel|Hyper-Threading}} is disabled and 2.2 W when enabled. Model price includes the {{intel|Poulsbo|chipset|l=chipset}}. |
== Cache == | == Cache == | ||
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|avx=No | |avx=No | ||
|avx2=No | |avx2=No | ||
− | + | ||
|abm=No | |abm=No | ||
|tbm=No | |tbm=No | ||
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[[File:Silverthorne die shot (marked).png|650px]] | [[File:Silverthorne die shot (marked).png|650px]] | ||
+ | |||
+ | == Documents == | ||
+ | === Datasheet === | ||
+ | * [[:File:atom z5xx.pdf|Intel Atom Processor Z5xx Series Datasheet]], June 2010 | ||
+ | * [[:File:atom z5xx update.pdf|Intel Atom Processor Z5xx Series Datasheet Specification Update]], July 2014 | ||
+ | |||
+ | === Other === | ||
+ | * [[:File:atom z5xx product brief.pdf|Atom Z5xx Product Brief]], 2008 |
Latest revision as of 16:14, 13 December 2017
Edit Values | |||||||||
Atom Z520 | |||||||||
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Silverthorne chip | |||||||||
General Info | |||||||||
Designer | Intel | ||||||||
Manufacturer | Intel | ||||||||
Model Number | Z520 | ||||||||
Part Number | AC80566UE014DW | ||||||||
S-Spec | SLB2H QEQS (QS) | ||||||||
Market | Mobile | ||||||||
Introduction | April 2, 2008 (announced) April 2, 2008 (launched) | ||||||||
Release Price | $65 | ||||||||
Shop | Amazon | ||||||||
General Specs | |||||||||
Family | Atom | ||||||||
Series | Z500 | ||||||||
Locked | Yes | ||||||||
Frequency | 1,333.33 MHz | ||||||||
Bus type | FSB | ||||||||
Bus speed | 133.33 MHz | ||||||||
Bus rate | 533.33 MT/s | ||||||||
Clock multiplier | 10 | ||||||||
CPUID | 106C2 | ||||||||
Microarchitecture | |||||||||
ISA | x86-32 (x86) | ||||||||
Microarchitecture | Bonnell | ||||||||
Platform | Menlow | ||||||||
Chipset | Poulsbo | ||||||||
Core Name | Silverthorne | ||||||||
Core Family | 6 | ||||||||
Core Model | 28 | ||||||||
Core Stepping | C0 | ||||||||
Process | 45 nm | ||||||||
Transistors | 47,212,207 | ||||||||
Technology | CMOS | ||||||||
Die | 24.18 mm² 7.8 mm × 3.1 mm | ||||||||
Word Size | 32 bit | ||||||||
Cores | 1 | ||||||||
Threads | 2 | ||||||||
Multiprocessing | |||||||||
Max SMP | 1-Way (Uniprocessor) | ||||||||
Electrical | |||||||||
Power dissipation (average) | 220 mW | ||||||||
Power (idle) | 100 mW | ||||||||
Vcore | 0.75 V-1.1 V | ||||||||
SDP | 960 mW | ||||||||
TDP | 2 W | ||||||||
Tjunction | 0 °C – 90 °C | ||||||||
Tcase | 0 °C – 70 °C | ||||||||
Tstorage | -40 °C – 85 °C | ||||||||
Packaging | |||||||||
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Z520 is an ultra-low power 32-bit x86 microprocessor introduced by Intel in early 2008 specifically for Mobile Internet Devices (MID). The Z520, which is based on the Bonnell microarchitecture (Silverthorne core), is manufactured on a 45 nm process. This processor operates at 1.33 Ghz with a TDP of just 2 W and an average power of 220 mW. The MPU features a legacy 533 MT/s front-side bus capable of communicating with the Poulsbo chipset in both low-power CMOS mode as well as normal GTL mode (which also works with other chipsets).
This processor has a TDP of 2 W when Hyper-Threading is disabled and 2.2 W when enabled. Model price includes the chipset.
Contents
Cache[edit]
- Main article: Bonnell § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
This processor has no integrated memory controller.
Graphics[edit]
This processor has no integrated graphics.
Features[edit]
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Die Shot[edit]
- See also: Bonnell § Silverthorne Die
- 45 nm process
- 9 metal layers
- 47,212,207 transistors
- 3.1 mm x 7.8 mm
- 24.18 mm² die size
Documents[edit]
Datasheet[edit]
- Intel Atom Processor Z5xx Series Datasheet, June 2010
- Intel Atom Processor Z5xx Series Datasheet Specification Update, July 2014
Other[edit]
- Atom Z5xx Product Brief, 2008
has feature | Hyper-Threading Technology +, Enhanced SpeedStep Technology + and Intel VT-x + |
has intel enhanced speedstep technology | true + |
has intel vt-x technology | true + |
has simultaneous multithreading | true + |
l1$ size | 56 KiB (57,344 B, 0.0547 MiB) + |
l1d$ description | 6-way set associative + |
l1d$ size | 24 KiB (24,576 B, 0.0234 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |