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Difference between revisions of "loongson/godson 2/2h"
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{{loongson title|Godson-2H}}
 
{{loongson title|Godson-2H}}
−
{{mpu
+
{{chip
 
| name                = Godson-2H
 
| name                = Godson-2H
 
| image              = godson-2h.jpg
 
| image              = godson-2h.jpg
Line 9: Line 9:
 
| model number        = 2H
 
| model number        = 2H
 
| part number        =  
 
| part number        =  
−
| part number 1       =  
+
| part number 2       =  
 
| market              = Desktop
 
| market              = Desktop
 
| first announced    = August, 2010
 
| first announced    = August, 2010
Line 23: Line 23:
 
| frequency 2        =  
 
| frequency 2        =  
 
| frequency N        =  
 
| frequency N        =  
−
| bus type            = <!-- (Property::bus type) -->
+
| bus type            = HyperTransport 1.03
−
| bus speed          = <!-- (Property::bus speed) -->
+
| bus speed          = 800 MHz
−
| bus rate            = <!-- (Property::bus rate) -->
+
| bus rate            =  
−
| bus links          = <!-- ?x bus rate -->
+
| bus links          =  
−
| clock multiplier    =
+
| clock multiplier    =  
  
 
| isa family          = MIPS
 
| isa family          = MIPS
 
| isa                = MIPS64
 
| isa                = MIPS64
−
| microarch          = GS464
+
| microarch          = GS464V
 
| platform            =  
 
| platform            =  
 
| chipset            =  
 
| chipset            =  
−
| core name          = GS464
+
| core name          = GS464V
 
| core family        =  
 
| core family        =  
 
| core model          =  
 
| core model          =  
 
| core stepping      =  
 
| core stepping      =  
 
| process            = 65 nm
 
| process            = 65 nm
−
| transistors        =  
+
| transistors        = 152,000,000
 
| technology          = CMOS
 
| technology          = CMOS
−
| die area            =  
+
| die area            = 117 mm²
 
| die width          =  
 
| die width          =  
 
| die length          =  
 
| die length          =  
Line 50: Line 50:
 
| max memory          =  
 
| max memory          =  
  
−
| electrical          = Yes
+
 
−
| power              = 5 W
+
| power              = 10 W
 
| v core              =  
 
| v core              =  
 
| v core tolerance    = <!-- OR ... -->
 
| v core tolerance    = <!-- OR ... -->
Line 78: Line 78:
 
| tambient max        =  
 
| tambient max        =  
  
−
| packaging          = <!-- put Yes if packaging info is added -->
+
| packaging          = Yes
−
| package 0          =  
+
| package 0          = FCBGA-741
−
| package 0 type      =  
+
| package 0 type      = FCBGA
−
| package 0 pins      =  
+
| package 0 pins      = 741
 
| package 0 pitch    =  
 
| package 0 pitch    =  
−
| package 0 width    =  
+
| package 0 width    = 31 mm
−
| package 0 length    =  
+
| package 0 length    = 31 mm
 
| package 0 height    =  
 
| package 0 height    =  
−
| socket 0            =  
+
| socket 0            = BGA-741
−
| socket 0 type      =  
+
| socket 0 type      = BGA
 +
}}
 +
'''Godson-2H''' ('''龙芯2H''') is a {{arch|64}} [[MIPS]] performance processor developed by [[Institute of Computing Technology of the Chinese Academy of Sciences|ICT]] and later [[Loongson]] for desktop computers. Introduced in late-[[2010]], the Godson-2H operates at up to 1 GHz consuming up to 10 W. This chip was manufactured on [[STMicroelectronics]]' [[65 nm process]].
 +
 
 +
The Godson-2H is actually a complete [[system on a chip]] incorporating the [[northbridge]] along with the [[southbridge]] on-die. Additionally the Godson-2H also incorporates a low-power [[Vivante]] {{vivante|GC800}} [[IGP]] operating at 400 MHz.
 +
 
 +
In addition to a standalone SoC, the Godson-2H can also operate in slave-mode serving as a cooperative [[southbridge]] to the more powerful {{\\\|Godson 3}} multi-core processor family.
 +
 
 +
== Cache ==
 +
{{main|loongson/microarchitectures/GS464V#Memory_Hierarchy|l1=GS464V § Cache}}
 +
{{cache size
 +
|l1 cache=128 KiB
 +
|l1i cache=64 KiB
 +
|l1i break=1x64 KiB
 +
|l1i desc=4-way set associative
 +
|l1d cache=64 KiB
 +
|l1d break=1x64 KiB
 +
|l1d desc=4-way set associative
 +
|l1d policy=
 +
|l2 cache=512 KiB
 +
|l2 break=1x512 KiB
 +
|l2 desc=4-way set associative
 +
|l2 policy=
 +
}}
 +
 
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR3-800
 +
|ecc=Yes
 +
|max mem=4 GiB
 +
|controllers=1
 +
|channels=1
 +
|max bandwidth=11.92 GiB/s
 +
|bandwidth schan=11.92 GiB/s
 +
}}
 +
 
 +
== Graphics ==
 +
{{integrated graphics
 +
| gpu                = GC800
 +
| device id          =
 +
| designer            = Vivante
 +
| execution units    = 4
 +
| max displays        =
 +
| max memory          =
 +
| frequency          = 400 MHz
 +
| max frequency      =
 +
 
 +
| output crt          = Yes
 +
| output sdvo        = Yes
 +
| output dsi          =
 +
| output edp          =
 +
| output dp          =
 +
| output hdmi        =
 +
| output vga          = Yes
 +
| output dvi          =
 +
 
 +
| directx ver        = 11
 +
| opengl ver        = 3.0
 +
| opencl ver        = 1.1
 +
| opengl es ver      = 2.0
 +
| hdmi ver          =
 +
| dp ver            =
 +
| edp ver            =
 +
| max res hdmi      =
 +
| max res hdmi freq  =
 +
| max res dp        =
 +
| max res dp freq    =
 +
| max res edp        =
 +
| max res edp freq  =
 +
| max res vga        = 1920x1080
 +
| max res vga freq  =
 +
| max res dsi        = 1920x1080
 +
| max res dsi freq  =  
 
}}
 
}}
−
'''Godson-2H''' is a {{arch|64}} [[MIPS]] performance processor developed by [[Institute of Computing Technology of the Chinese Academy of Sciences|ICT]] and later [[Loongson]] for desktop computers. Introduced in late-[[2010]], the Godson-2H operates at up to 1 GHz consuming 5 W. This chip was manufactured on [[STMicroelectronics]]' [[65 nm process]].
+
 
 +
== Expansions ==
 +
This chip has integrated [[HyperTransport]] 1.03 operating at 200, 400, or 800 MHz.
 +
{{expansions
 +
|pcie revision=2.0
 +
|pcie lanes=4
 +
|pcie config=1x4
 +
|pcie config 2=4x1
 +
|usb revision=2.0
 +
|usb ports=6
 +
|sata revision=2
 +
|sata ports=2
 +
|lpc revision=1.1
 +
|i2c=Yes
 +
|i2c ports=2
 +
|uart ports=1
 +
|jtag=Yes
 +
|gp io=16 lines
 +
}}
 +
 
 +
== Networking ==
 +
{{network
 +
|mii opts=Yes
 +
|rgmii=Yes
 +
|spi opts=Yes
 +
}}
 +
 
 +
== Die Shot ==
 +
* [[65 nm process]]
 +
* 152,000,000 transistors
 +
* 117 mm² die size
 +
[[File:godson-2h die shot.png|800px]]
 +
 
 +
== References ==
 +
* Xiao, Bin, et al. "Godson-2H: a complex low power SOC in 65nm CMOS." Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on. IEEE, 2012.
 +
* Loongson Technology, "龙芯芯片产品技术白皮书" ("Godson chip product technology white paper")

Latest revision as of 15:31, 13 December 2017

Edit Values
Godson-2H
godson-2h.jpg
Godson-2H chip
General Info
DesignerLoongson
ManufacturerSTMicroelectronics
Model Number2H
MarketDesktop
IntroductionAugust, 2010 (announced)
March, 2011 (launched)
General Specs
FamilyGodson 2
SeriesGodson 2
Frequency1,000 MHz
Bus typeHyperTransport 1.03
Bus speed800 MHz
Microarchitecture
ISAMIPS64 (MIPS)
MicroarchitectureGS464V
Core NameGS464V
Process65 nm
Transistors152,000,000
TechnologyCMOS
Die117 mm²
Word Size64 bit
Cores1
Threads1
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Power dissipation10 W

Godson-2H (龙芯2H) is a 64-bit MIPS performance processor developed by ICT and later Loongson for desktop computers. Introduced in late-2010, the Godson-2H operates at up to 1 GHz consuming up to 10 W. This chip was manufactured on STMicroelectronics' 65 nm process.

The Godson-2H is actually a complete system on a chip incorporating the northbridge along with the southbridge on-die. Additionally the Godson-2H also incorporates a low-power Vivante GC800 IGP operating at 400 MHz.

In addition to a standalone SoC, the Godson-2H can also operate in slave-mode serving as a cooperative southbridge to the more powerful Godson 3 multi-core processor family.

Cache[edit]

Main article: GS464V § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
1x64 KiB4-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
1x64 KiB4-way set associative 
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  1x512 KiB4-way set associative 

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-800
Supports ECCYes
Max Mem4 GiB
Controllers1
Channels1
Max Bandwidth11.92 GiB/s
12,206.08 MiB/s
12.799 GB/s
12,799.003 MB/s
0.0116 TiB/s
0.0128 TB/s
Bandwidth
Single 11.92 GiB/s

Graphics[edit]

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUGC800
DesignerVivante
Execution Units4
Frequency400 MHz
0.4 GHz
400,000 KHz
OutputVGA, SDVO, CRT
Max Resolution
DSI1920x1080
VGA1920x1080
Standards
DirectX11
OpenGL3.0
OpenCL1.1
OpenGL ES2.0

Expansions[edit]

This chip has integrated HyperTransport 1.03 operating at 200, 400, or 800 MHz.

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision2.0
Max Lanes4
Configs1x4, 4x1
USB
Revision2.0
Ports6
SATA
Revision2
Ports2
LPC
Revision1.1
I²C
Ports2
GP I/O16 lines
JTAGYes


Networking[edit]

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
MII
RGMIIYes

Die Shot[edit]

godson-2h die shot.png

References[edit]

  • Xiao, Bin, et al. "Godson-2H: a complex low power SOC in 65nm CMOS." Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on. IEEE, 2012.
  • Loongson Technology, "龙芯芯片产品技术白皮书" ("Godson chip product technology white paper")
Retrieved from "https://en.wikichip.org/w/index.php?title=loongson/godson_2/2h&oldid=71131"
Facts about "Godson-2H - Loongson"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Godson-2H - Loongson#io +
base frequency1,000 MHz (1 GHz, 1,000,000 kHz) +
bus speed800 MHz (0.8 GHz, 800,000 kHz) +
bus typeHyperTransport 1.03 +
core count1 +
core nameGS464V +
designerLoongson +
die area117 mm² (0.181 in², 1.17 cm², 117,000,000 µm²) +
familyGodson 2 +
first announcedAugust 2010 +
first launchedMarch 2011 +
full page nameloongson/godson 2/2h +
has ecc memory supporttrue +
instance ofmicroprocessor +
integrated gpuGC800 +
integrated gpu base frequency400 MHz (0.4 GHz, 400,000 KHz) +
integrated gpu designerVivante +
integrated gpu execution units4 +
isaMIPS64 +
isa familyMIPS +
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ description4-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description4-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description4-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
ldateMarch 2011 +
main imageFile:godson-2h.jpg +
main image captionGodson-2H chip +
manufacturerSTMicroelectronics +
market segmentDesktop +
max cpu count1 +
max memory bandwidth11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels1 +
max pcie lanes4 +
microarchitectureGS464V +
model number2H +
nameGodson-2H +
power dissipation10 W (10,000 mW, 0.0134 hp, 0.01 kW) +
process65 nm (0.065 μm, 6.5e-5 mm) +
seriesGodson 2 +
smp max ways1 +
supported memory typeDDR3-800 +
technologyCMOS +
thread count1 +
transistor count152,000,000 +
word size64 bit (8 octets, 16 nibbles) +