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Difference between revisions of "loongson/godson 2/2g"
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{{loongson title|Godson-2G}}
 
{{loongson title|Godson-2G}}
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{{mpu
+
{{chip
 
| name                = Godson-2G
 
| name                = Godson-2G
 
| image              = godson-2g.jpg
 
| image              = godson-2g.jpg
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| model number        = 2G
 
| model number        = 2G
 
| part number        =  
 
| part number        =  
−
| part number 1       =  
+
| part number 2       =  
 
| market              = Desktop
 
| market              = Desktop
 
| first announced    = April, 2009
 
| first announced    = April, 2009
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| family              = Godson 2
 
| family              = Godson 2
 
| series              = Godson 2
 
| series              = Godson 2
−
| locked              = No
+
| locked              =  
 
| frequency          = 1,000 MHz
 
| frequency          = 1,000 MHz
 
| frequency 2        =  
 
| frequency 2        =  
 
| frequency N        =  
 
| frequency N        =  
−
| bus type            = <!-- (Property::bus type) -->
+
| bus type            = HyperTransport 1.0
−
| bus speed          = <!-- (Property::bus speed) -->
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| bus speed          = 400 MHz
−
| bus rate            = <!-- (Property::bus rate) -->
+
| bus rate            =  
−
| bus links          = <!-- ?x bus rate -->
+
| bus links          =  
−
| clock multiplier    =
+
| clock multiplier    = 2.5
  
 
| isa family          = MIPS
 
| isa family          = MIPS
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| core stepping      =  
 
| core stepping      =  
 
| process            = 65 nm
 
| process            = 65 nm
−
| transistors        =  
+
| transistors        = 100,000,000
 
| technology          = CMOS
 
| technology          = CMOS
 
| die area            = 53.54 mm²
 
| die area            = 53.54 mm²
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| max memory          =  
 
| max memory          =  
  
−
| electrical          = Yes
+
 
−
| power              = 4 W
+
| power              = 3 W
 
| v core              =  
 
| v core              =  
 
| v core tolerance    = <!-- OR ... -->
 
| v core tolerance    = <!-- OR ... -->
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| packaging          = Yes
 
| packaging          = Yes
−
| package 0          = FCBGA-888
+
| package 0          = FCBGA-741
 
| package 0 type      = FCBGA
 
| package 0 type      = FCBGA
−
| package 0 pins      = 888
+
| package 0 pins      = 741
 
| package 0 pitch    =  
 
| package 0 pitch    =  
−
| package 0 width    =  
+
| package 0 width    = 31 mm
−
| package 0 length    =  
+
| package 0 length    = 31 mm
 
| package 0 height    =  
 
| package 0 height    =  
−
| socket 0            = BGA-888
+
| socket 0            = BGA-741
 
| socket 0 type      = BGA
 
| socket 0 type      = BGA
 
}}
 
}}
−
'''Godson-2G''' is a {{arch|64}} [[MIPS]] performance processor developed by [[Institute of Computing Technology of the Chinese Academy of Sciences|ICT]] and later [[Loongson]] for desktop computers. Introduced in late-[[2010]], the Godson-2G operates at up to 1 GHz consuming up to 4 W. This chip was manufactured on [[STMicroelectronics]]' [[65 nm process]].
+
'''Godson-2G''' ('''龙芯2G''') is a {{arch|64}} [[MIPS]] performance processor developed by [[Institute of Computing Technology of the Chinese Academy of Sciences|ICT]] and later [[Loongson]] for desktop computers. Introduced in late-[[2010]], the Godson-2G operates at up to 1 GHz consuming up to 3 W. This chip was manufactured on [[STMicroelectronics]]' [[65 nm process]].
 +
 
 +
This specific models incorporates a considerably larger [[2nd level cache]] compared to the rest of the {{\\\|Godson 2}} family along with an extended number of additional interfaces in a relatively large package. The Godson-2G integrates the majority of the [[southbridge]] on-die.
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 +
== Cache ==
 +
{{main|loongson/microarchitectures/GS464#Memory_Hierarchy|l1=GS464 § Cache}}
 +
{{cache size
 +
|l1 cache=128 KiB
 +
|l1i cache=64 KiB
 +
|l1i break=1x64 KiB
 +
|l1i desc=4-way set associative
 +
|l1d cache=64 KiB
 +
|l1d break=1x64 KiB
 +
|l1d desc=4-way set associative
 +
|l1d policy=
 +
|l2 cache=1 MiB
 +
|l2 break=1x1 MiB
 +
|l2 desc=4-way set associative
 +
|l2 policy=
 +
}}
 +
 
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR3-800
 +
|ecc=Yes
 +
|max mem=4 GiB
 +
|controllers=1
 +
|channels=1
 +
|max bandwidth=11.92 GiB/s
 +
|bandwidth schan=11.92 GiB/s
 +
}}
 +
 
 +
== Expansions ==
 +
This chip has integrated [[HyperTransport]] 1.0 operating at 400 MHz.
 +
{{expansions
 +
|pci width  = 32 bit
 +
|pci clock = 66 MHz
 +
|pcix width = 32 bit
 +
|pcix clock = 133 MHz
 +
|lpc revision=1.1
 +
}}
 +
 
 +
== Die Shot ==
 +
* [[65 nm process]]
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* 100,000,000 transistors
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* 53.54 mm² die size
 +
[[File:godson-2g die shot.png|700px]]
  
 
== References ==
 
== References ==
 
* Zhao, Ji-Ye, et al. "Physical Design Methodology for Godson-2G Microprocessor." Journal of Computer Science and Technology 25.2 (2010): 225-231.
 
* Zhao, Ji-Ye, et al. "Physical Design Methodology for Godson-2G Microprocessor." Journal of Computer Science and Technology 25.2 (2010): 225-231.
 +
* Weiwu Hu, Yunji Chen. "GS464V: A High-Performance Low-Power XPU with 512-Bit Vector Extension". HotChips 22 (2010).
 +
* Loongson Technology, "龙芯芯片产品技术白皮书" ("Godson chip product technology white paper")

Latest revision as of 15:31, 13 December 2017

Edit Values
Godson-2G
godson-2g.jpg
Godson-2G chip
General Info
DesignerLoongson
ManufacturerSTMicroelectronics
Model Number2G
MarketDesktop
IntroductionApril, 2009 (announced)
November, 2010 (launched)
General Specs
FamilyGodson 2
SeriesGodson 2
Frequency1,000 MHz
Bus typeHyperTransport 1.0
Bus speed400 MHz
Clock multiplier2.5
Microarchitecture
ISAMIPS64 (MIPS)
MicroarchitectureGS464
Core NameGS464
Process65 nm
Transistors100,000,000
TechnologyCMOS
Die53.54 mm²
Word Size64 bit
Cores1
Threads1
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Power dissipation3 W

Godson-2G (龙芯2G) is a 64-bit MIPS performance processor developed by ICT and later Loongson for desktop computers. Introduced in late-2010, the Godson-2G operates at up to 1 GHz consuming up to 3 W. This chip was manufactured on STMicroelectronics' 65 nm process.

This specific models incorporates a considerably larger 2nd level cache compared to the rest of the Godson 2 family along with an extended number of additional interfaces in a relatively large package. The Godson-2G integrates the majority of the southbridge on-die.

Cache[edit]

Main article: GS464 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
1x64 KiB4-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
1x64 KiB4-way set associative 
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  1x1 MiB4-way set associative 

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-800
Supports ECCYes
Max Mem4 GiB
Controllers1
Channels1
Max Bandwidth11.92 GiB/s
12,206.08 MiB/s
12.799 GB/s
12,799.003 MB/s
0.0116 TiB/s
0.0128 TB/s
Bandwidth
Single 11.92 GiB/s

Expansions[edit]

This chip has integrated HyperTransport 1.0 operating at 400 MHz.

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCI
Width32 bit
Clock66 MHz
PCI-X
Width32 bit
Clock133 MHz
LPC
Revision1.1


Die Shot[edit]

godson-2g die shot.png

References[edit]

  • Zhao, Ji-Ye, et al. "Physical Design Methodology for Godson-2G Microprocessor." Journal of Computer Science and Technology 25.2 (2010): 225-231.
  • Weiwu Hu, Yunji Chen. "GS464V: A High-Performance Low-Power XPU with 512-Bit Vector Extension". HotChips 22 (2010).
  • Loongson Technology, "龙芯芯片产品技术白皮书" ("Godson chip product technology white paper")
Retrieved from "https://en.wikichip.org/w/index.php?title=loongson/godson_2/2g&oldid=71130"
Facts about "Godson-2G - Loongson"
RDF feed
base frequency1,000 MHz (1 GHz, 1,000,000 kHz) +
bus speed400 MHz (0.4 GHz, 400,000 kHz) +
bus typeHyperTransport 1.0 +
clock multiplier2.5 +
core count1 +
core nameGS464 +
designerLoongson +
die area53.54 mm² (0.083 in², 0.535 cm², 53,540,000 µm²) +
familyGodson 2 +
first announcedApril 2009 +
first launchedNovember 2010 +
full page nameloongson/godson 2/2g +
has ecc memory supporttrue +
instance ofmicroprocessor +
isaMIPS64 +
isa familyMIPS +
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ description4-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description4-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description4-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
ldateNovember 2010 +
main imageFile:godson-2g.jpg +
main image captionGodson-2G chip +
manufacturerSTMicroelectronics +
market segmentDesktop +
max cpu count1 +
max memory bandwidth11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels1 +
microarchitectureGS464 +
model number2G +
nameGodson-2G +
power dissipation3 W (3,000 mW, 0.00402 hp, 0.003 kW) +
process65 nm (0.065 μm, 6.5e-5 mm) +
seriesGodson 2 +
smp max ways1 +
supported memory typeDDR3-800 +
technologyCMOS +
thread count1 +
transistor count100,000,000 +
word size64 bit (8 octets, 16 nibbles) +