From WikiChip
Difference between revisions of "samsung/exynos/3110"
< samsung‎ | exynos

 
(6 intermediate revisions by 3 users not shown)
Line 1: Line 1:
 
{{samsung title|Exynos 3110}}
 
{{samsung title|Exynos 3110}}
−
{{mpu
+
{{chip
−
| name               = Exynos 3110
+
|name=Exynos 3110
−
| no image           = Yes
+
|no image=Yes
−
| image              =
+
|designer=Samsung
−
| image size          =
+
|designer 2=ARM Holdings
−
| caption            =  
+
|manufacturer=Samsung
−
| designer           = ARM Holdings
+
|model number=3110
−
| designer 2          = Samsung
+
|market=Mobile
−
| manufacturer       = Samsung
+
|first announced=March 23, 2010
−
| model number       = 3110
+
|first launched=March 23, 2010
−
| part number        =
+
|family=Exynos
−
| part number 1      =
+
|series=Exynos 3
−
| part number 2      =
+
|frequency=1,000 MHz
−
| part number 3      =
+
|bus type=AXI
−
| market             = Mobile
+
|isa=ARMv7
−
| first announced     = March 23, 2010
+
|isa family=ARM
−
| first launched     = March 23, 2010
+
|microarch=Cortex-A8
−
| last order          =
+
|core name=Cortex-A8
−
| last shipment      =
+
|process=45 nm
−
| release price      =
+
|technology=CMOS
−
 
+
|word size=32 bit
−
| family             = Exynos
+
|core count=1
−
| series             = Exynos 3
+
|thread count=1
−
| locked              =
+
|max cpus=1
−
| frequency           = 1,000 MHz
+
|max memory=512 MiB
−
| bus type           = AXI
+
|packaging=Yes
−
| bus speed          =  
+
|package 0=FBGA
−
| bus rate            =
+
|package 0 type=FBGA
−
| bus links          =
+
|package 0 pitch=0.65 mm
−
| clock multiplier    =
+
|package 0 width=17 mm
−
 
+
|package 0 length=17 mm
−
| isa family         = ARM
 
−
| isa                = ARMv7
 
−
| microarch           = Cortex-A8
 
−
| platform            =
 
−
| chipset            =
 
−
| core name           = Cortex-A8
 
−
| core family        =
 
−
| core model          =
 
−
| core stepping      =
 
−
| process             = 45 nm
 
−
| transistors        =
 
−
| technology         = CMOS
 
−
| die area            =
 
−
| die width          =
 
−
| die length          =
 
−
| word size           = 32 bit
 
−
| core count         = 1
 
−
| thread count       = 1
 
−
| max cpus           = 1
 
−
| max memory         = 512 MiB
 
−
| max memory addr    =
 
−
 
 
−
| electrical          =
 
−
| power              =
 
−
| v core              =
 
−
| v core tolerance    = <!-- OR ... -->
 
−
| v core min          =
 
−
| v core max          =
 
−
| v io                =
 
−
| v io tolerance      =
 
−
| v io 2              = <!-- OR ... -->
 
−
| v io 3              =
 
−
| sdp                =
 
−
| tdp                =
 
−
| tdp typical        =
 
−
| ctdp down          =
 
−
| ctdp down frequency =
 
−
| ctdp up            =
 
−
| ctdp up frequency  =
 
−
| temp min            = <!-- use TJ/TC whenever possible instead -->
 
−
| temp max            =
 
−
| tjunc min          = <!-- .. °C -->
 
−
| tjunc max          =
 
−
| tcase min          =
 
−
| tcase max          =
 
−
| tstorage min        =
 
−
| tstorage max        =
 
−
| tambient min        =
 
−
| tambient max        =
 
−
 
 
−
| packaging           = Yes
 
−
| package 0           = FBGA
 
−
| package 0 type     = FBGA
 
−
| package 0 pins      =
 
−
| package 0 pitch     = 0.65 mm
 
−
| package 0 width     = 17 mm
 
−
| package 0 length   = 17 mm
 
−
| package 0 height    =
 
−
| socket 0            =
 
−
| socket 0 type      =
 
 
}}
 
}}
−
'''Exynos 3110''' is a [[single-core]] {{arch|32}} performance [[ARM]] system on a chip introduced by [[Samsung]] in [[2010]]. The Exynos 3110 was the first model from the {{samsung|Exynos}} family which found its way into many of Samsung's and Google's devices including the Galaxy S line, Galaxy Tab, and the Nexus S. The Exynos 3110 incorporates a {{armh|Cortex-A8}} core operating at 1 GHz along with a {{imgtec|PowerVR SGX540}} [[IGP]] operating at 200 MHz. This SoC supports up to LPDDR2-400 dual-channel memory.
+
'''Exynos 3110''' (formerly '''[[former name::S5PC110]]''') is a [[single-core]] {{arch|32}} performance [[ARM]] system on a chip introduced by [[Samsung]] in [[2010]]. The Exynos 3110 was the first model from the {{samsung|Exynos}} family which found its way into many of Samsung's and Google's devices including the Galaxy S line, Galaxy Tab, and the Nexus S. The Exynos 3110 incorporates a {{armh|Cortex-A8|l=arch}} core operating at 1 GHz along with a {{imgtec|PowerVR SGX540}} [[IGP]] operating at 200 MHz. This SoC supports up to LPDDR2-400 dual-channel memory.
  
 
== Cache ==
 
== Cache ==
Line 145: Line 85:
 
| execution units    = 1
 
| execution units    = 1
 
| max displays        = 1
 
| max displays        = 1
−
| max memory          = 2 GiB
+
| max memory          = 512 MiB
 
| frequency          = 400 MHz
 
| frequency          = 400 MHz
 
| max frequency      =  
 
| max frequency      =  
Line 241: Line 181:
  
 
{{expand list}}
 
{{expand list}}
 +
 +
== Diagram ==
 +
[[File:ex3110 block.png|900px]]
 +
 +
== Documents ==
 +
=== Datasheets ===
 +
* [[:File:Exynos 3110.pdf|Exynos 3110]]

Latest revision as of 20:28, 27 March 2018

Edit Values
Exynos 3110
General Info
DesignerSamsung,
ARM Holdings
ManufacturerSamsung
Model Number3110
MarketMobile
IntroductionMarch 23, 2010 (announced)
March 23, 2010 (launched)
General Specs
FamilyExynos
SeriesExynos 3
Frequency1,000 MHz
Bus typeAXI
Microarchitecture
ISAARMv7 (ARM)
MicroarchitectureCortex-A8
Core NameCortex-A8
Process45 nm
TechnologyCMOS
Word Size32 bit
Cores1
Threads1
Max Memory512 MiB
Multiprocessing
Max SMP1-Way (Uniprocessor)

Exynos 3110 (formerly S5PC110) is a single-core 32-bit performance ARM system on a chip introduced by Samsung in 2010. The Exynos 3110 was the first model from the Exynos family which found its way into many of Samsung's and Google's devices including the Galaxy S line, Galaxy Tab, and the Nexus S. The Exynos 3110 incorporates a Cortex-A8 core operating at 1 GHz along with a PowerVR SGX540 IGP operating at 200 MHz. This SoC supports up to LPDDR2-400 dual-channel memory.

Cache[edit]

Main article: Cortex-A8 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$64 KiB
65,536 B
0.0625 MiB
L1I$32 KiB
32,768 B
0.0313 MiB
1x32 KiB  
L1D$32 KiB
32,768 B
0.0313 MiB
1x32 KiB  
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  1x512 KiB  

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR2-400
Supports ECCNo
Max Mem512 MiB
Controllers1
Channels2
Max Bandwidth5.96 GiB/s
6,103.04 MiB/s
6.4 GB/s
6,399.501 MB/s
0.00582 TiB/s
0.0064 TB/s
Bandwidth
Single 2.98 GiB/s
Double 5.96 GiB/s
  • Flash: OneNAND 512MB
  • Micro-SD slot (2GB bundle)
  • Standard SDHC slot

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
USB
Revision2.0
Ports2
FeaturesHost + OTG
UART
Ports3


Graphics[edit]

The PowerVR SGX540 is capable of up to 20M triangles/s and 1000M pixels/s.

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUPowerVR SGX540
DesignerImagination Technologies
Execution Units1Max Displays1
Max Memory512 MiB
524,288 KiB
536,870,912 B
0.5 GiB
Frequency400 MHz
0.4 GHz
400,000 KHz
OutputHDMI, VGA
Max Resolution
LVDS1366x768
Standards
DirectX10.1
OpenGL2.1
OpenGL ES2.0
HDMI1.0

Wireless[edit]

  • UMTS 850/1900/2100
  • GSM 850/900/1800/1900MHz, HSPA+ up to 21.1 Mbps
Antu network-wireless-connected-100.svgWireless Communications
Wi-Fi
WiFi
802.11aYes
802.11bYes
802.11gYes
802.11nYes
Cellular
2G
GSM Yes
GPRS Yes
3G
UMTS
HSDPAYes

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
Thumb-2Thumb-2 Extension
VFPv3Vector Floating Point (VFP) v3 Extension
NEONAdvanced SIMD extension

Utilizing devices[edit]

  • Samsung Galaxy SL
  • Samsung Galaxy S
  • Samsung Galaxy S Vibrant
  • Samsung Galaxy S
  • Samsung Wave S8500
  • Samsung Wave II S8530
  • Samsung Galaxy Tab
  • Samsung Droid Charge
  • Samsung Exhibit 4G
  • Samsung Stratosphere
  • Google Nexus S
  • Meizu M9

This list is incomplete; you can help by expanding it.

Diagram[edit]

ex3110 block.png

Documents[edit]

Datasheets[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=samsung/exynos/3110&oldid=75583"
Facts about "Exynos 3110 - Samsung"
RDF feed
base frequency1,000 MHz (1 GHz, 1,000,000 kHz) +
bus typeAXI +
core count1 +
core nameCortex-A8 +
designerSamsung + and ARM Holdings +
familyExynos +
first announcedMarch 23, 2010 +
first launchedMarch 23, 2010 +
former nameS5PC110 +
full page namesamsung/exynos/3110 +
has 2g supporttrue +
has 3g supporttrue +
has ecc memory supportfalse +
has gprs supporttrue +
has gsm supporttrue +
has hsdpa supporttrue +
has umts supporttrue +
instance ofmicroprocessor +
integrated gpuPowerVR SGX540 +
integrated gpu base frequency400 MHz (0.4 GHz, 400,000 KHz) +
integrated gpu designerImagination Technologies +
integrated gpu execution units1 +
integrated gpu max memory512 MiB (524,288 KiB, 536,870,912 B, 0.5 GiB) +
isaARMv7 +
isa familyARM +
l1$ size64 KiB (65,536 B, 0.0625 MiB) +
l1d$ size32 KiB (32,768 B, 0.0313 MiB) +
l1i$ size32 KiB (32,768 B, 0.0313 MiB) +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
ldateMarch 23, 2010 +
manufacturerSamsung +
market segmentMobile +
max cpu count1 +
max memory512 MiB (524,288 KiB, 536,870,912 B, 0.5 GiB, 4.882812e-4 TiB) +
max memory bandwidth5.96 GiB/s (6,103.04 MiB/s, 6.4 GB/s, 6,399.501 MB/s, 0.00582 TiB/s, 0.0064 TB/s) +
max memory channels2 +
microarchitectureCortex-A8 +
model number3110 +
nameExynos 3110 +
process45 nm (0.045 μm, 4.5e-5 mm) +
seriesExynos 3 +
smp max ways1 +
supported memory typeLPDDR2-400 +
technologyCMOS +
thread count1 +
used bySamsung Galaxy SL +, Samsung Galaxy S +, Samsung Galaxy S Vibrant +, Samsung Wave S8500 +, Samsung Wave II S8530 +, Samsung Galaxy Tab +, Samsung Droid Charge +, Samsung Exhibit 4G +, Samsung Stratosphere +, Google Nexus S + and Meizu M9 +
word size32 bit (4 octets, 8 nibbles) +