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From WikiChip
Difference between revisions of "ibm/microarchitectures/power6+"
< ibm
| Line 7: | Line 7: | ||
| introduction = 2008 | | introduction = 2008 | ||
| phase-out = | | phase-out = | ||
| − | | process = | + | | process = 65 nm |
| cores = | | cores = | ||
| cores 2 = | | cores 2 = | ||
Latest revision as of 05:09, 1 February 2017
| Edit Values | |
| POWER6+ µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | IBM |
| Manufacturer | IBM |
| Introduction | 2008 |
| Process | 65 nm |
| Pipeline | |
| Type | Superscalar |
| Speculative | Yes |
| Reg Renaming | Yes |
| Succession | |
POWER6+ is the Power microarchitecture for IBM's family of POWER6+ processors that was introduced in 2008. POWER6+ is an enhanced version and the successor to POWER6.
Retrieved from "https://en.wikichip.org/w/index.php?title=ibm/microarchitectures/power6%2B&oldid=38753"
Facts about "POWER6+ - Microarchitectures - IBM"
| codename | POWER6+ + |
| designer | IBM + |
| first launched | 2008 + |
| full page name | ibm/microarchitectures/power6+ + |
| instance of | microarchitecture + |
| manufacturer | IBM + |
| microarchitecture type | CPU + |
| name | POWER6+ + |
| process | 65 nm (0.065 μm, 6.5e-5 mm) + |