Semiconductor & Computer Engineering
-
WikiChip
WikiChip
-
Architectures
Popular x86
-
Intel
- Client
- Server
- Big Cores
- Small Cores
-
AMD
Popular ARM
-
ARM
- Server
- Big
- Little
-
Cavium
-
Samsung
-
-
Chips
Popular Families
-
Ampere
-
Apple
-
Cavium
-
HiSilicon
-
MediaTek
-
NXP
-
Qualcomm
-
Renesas
-
Samsung
-
From WikiChip
Difference between revisions of "intel/microarchitectures/modified pentium m"
< intel | microarchitectures
| Line 8: | Line 8: | ||
| phase-out = 2008 | | phase-out = 2008 | ||
| process = 65 nm | | process = 65 nm | ||
| + | |isa=x86-16 | ||
| + | |isa 2=x86-32 | ||
| succession = Yes | | succession = Yes | ||
Latest revision as of 18:26, 30 November 2017
| Edit Values | |
| Modified Pentium M µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | 2006 |
| Phase-out | 2008 |
| Process | 65 nm |
| Instructions | |
| ISA | x86-16, x86-32 |
| Succession | |
Modified Pentium M (though no official name was ever given by Intel) was the microarchitecture for Intel's Yonah core-based microprocessors. This miroarchitecture was a modified version of the original Pentium M microarchitecture.