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Difference between revisions of "intel/celeron/3865u"
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{{intel title|Celeron 3865U}}
 
{{intel title|Celeron 3865U}}
−
{{mpu
+
{{chip
−
| name               = Celeron 3865U
+
|name=Celeron 3865U
−
| no image           = Yes
+
|no image=Yes
−
| image              =
+
|designer=Intel
−
| image size          =
+
|manufacturer=Intel
−
| caption            =
+
|model number=3865U
−
| designer           = Intel
+
|s-spec=SR349
−
| manufacturer       = Intel
+
|market=Mobile
−
| model number       = 3865U
+
|first announced=January 3, 2017
−
| part number        =
+
|first launched=January 3, 2017
−
| part number 1      =
+
|family=Celeron
−
| s-spec             =  
+
|series=3800
−
| market             = Mobile
+
|locked=Yes
−
| first announced     = January 3, 2017
+
|frequency=1,800 MHz
−
| first launched     = January 3, 2017
+
|bus type=OPI
−
| last order          =
+
|bus rate=4 GT/s
−
| last shipment      =
+
|clock multiplier=22
−
| release price      =
+
|cpuid=806E9
−
 
+
|isa=x86-64
−
| family             = Celeron
+
|isa family=x86
−
| series             = 3800
+
|microarch=Kaby Lake
−
| locked             = Yes
+
|platform=Kaby Lake
−
| frequency           = 1,800 MHz
+
|core name=Kaby Lake U
−
| bus type           = OPI
+
|core family=6
−
| bus speed          =
+
|core model=142
−
| bus rate           = 4 GT/s
+
|core stepping=H0
−
| bus links          =
+
|process=14 nm
−
| clock multiplier   = 22
+
|technology=CMOS
−
| cpuid               = 306A9
+
|word size=64 bit
−
 
+
|core count=2
−
| isa family          = x86
+
|thread count=2
−
| isa                 = x86-64
+
|max cpus=1
−
| microarch           = Kaby Lake
+
|max memory=64 GiB
−
| platform           = Kaby Lake
+
|v core min=0.25 V
−
| chipset            =
+
|v core max=1.52 V
−
| chipset 2          =
+
|tdp=15 W
−
| core name           = Kaby Lake U
+
|ctdp down=10 W
−
| core family         = 6
+
|tjunc min=0 °C
−
| core model         = 58
+
|tjunc max=100 °C
−
| core stepping      =  
+
|tstorage min=-25 °C
−
| core stepping 2    =  
+
|tstorage max=125 °C
−
| process             = 14 nm
+
|package module 1={{packages/intel/fcbga-1356}}
−
| transistors        =
 
−
| technology         = CMOS
 
−
| die area            =
 
−
| die width          =
 
−
| die length          =
 
−
| word size           = 64 bit
 
−
| core count         = 2
 
−
| thread count       = 2
 
−
| max cpus           = 1
 
−
| max memory         = 64 GiB
 
−
 
 
−
| electrical          = Yes
 
−
| v core min         = 0.25 V
 
−
| v core max         = 1.52 V
 
−
| tdp                 = 15 W
 
−
| tdp typical        =
 
−
| ctdp down           = 10 W
 
−
| ctdp down frequency =
 
−
| ctdp up            =
 
−
| ctdp up frequency  =
 
−
| tjunc min           = 0 °C
 
−
| tjunc max           = 100 °C
 
−
| tcase min          =
 
−
| tcase max          =
 
−
| tstorage min       = -25 °C
 
−
| tstorage max       = 125 °C
 
−
| tambient min        =
 
−
| tambient max        =
 
−
 
 
−
| packaging          = Yes
 
−
| package           = FCBGA-1356
 
−
| package type      = FCBGA
 
−
| package pitch      = 0.65 mm
 
−
| package size      = 42 mm x 24 mm
 
−
| socket            = BGA-1356
 
−
| socket type        = BGA
 
 
}}
 
}}
−
'''Celeron 3865U''' is a {{arch|64}} [[dual-core]] budget [[x86]] mobile microprocessors introduced by [[Intel]] in early 2017. The 3865U, which is based on the {{intel|Kaby Lake|l=arch}} microarchitecture, is fabricated on Intel's improved [[14 nm|14nm+ process]]. This processor operates at 1.8 GHz and with a TDP of 15 W and supports up to 32 GiB of dual-channel non-ECC DDR4-2133. Additionally the 3865U incorporates Intel's {{intel|HD Graphics 610}} [[IGP]] operating at 300 MHz with a burst frequency of 900 GHz.
+
'''Celeron 3865U''' is a {{arch|64}} [[dual-core]] budget [[x86]] mobile microprocessors introduced by [[Intel]] in early 2017. The 3865U, which is based on the {{intel|Kaby Lake|l=arch}} microarchitecture, is fabricated on Intel's improved [[14 nm|14nm+ process]]. This processor operates at 1.8 GHz with a TDP of 15 W and supports up to 32 GiB of dual-channel non-ECC DDR4-2133. Additionally the 3865U incorporates Intel's {{intel|HD Graphics 610}} [[IGP]] operating at 300 MHz with a burst frequency of 900 GHz.
  
 +
This model has a configurable TDP-down of 10 W.
 
== Cache ==
 
== Cache ==
 
{{main|intel/microarchitectures/kaby_lake#Memory_Hierarchy|l1=Kaby Lake § Cache}}
 
{{main|intel/microarchitectures/kaby_lake#Memory_Hierarchy|l1=Kaby Lake § Cache}}
Line 88: Line 53:
 
|l1i break=2x32 KiB
 
|l1i break=2x32 KiB
 
|l1i desc=8-way set associative
 
|l1i desc=8-way set associative
−
|l1i policy=write-back
 
 
|l1d cache=64 KiB
 
|l1d cache=64 KiB
 
|l1d break=2x32 KiB
 
|l1d break=2x32 KiB
Line 134: Line 98:
 
| max displays        = 3
 
| max displays        = 3
 
| max memory          = 32 GiB
 
| max memory          = 32 GiB
−
| frequency          = 350 MHz
+
| frequency          = 300 MHz
 
| max frequency      = 900 MHz
 
| max frequency      = 900 MHz
  
Line 151: Line 115:
 
| hdmi ver          = 1.4a
 
| hdmi ver          = 1.4a
 
| dp ver            = 1.2
 
| dp ver            = 1.2
−
| edp ver            = 1.3
+
| edp ver            = 1.4
 
| max res hdmi      = 4096x2304
 
| max res hdmi      = 4096x2304
 
| max res hdmi freq  = 24 Hz
 
| max res hdmi freq  = 24 Hz
Line 169: Line 133:
 
| intel clear video    = Yes
 
| intel clear video    = Yes
 
| intel clear video hd = Yes
 
| intel clear video hd = Yes
 +
}}
 +
{{kaby lake hardware accelerated video table|col=1}}
 +
 +
== Features ==
 +
{{x86 features
 +
|real=Yes
 +
|protected=Yes
 +
|smm=Yes
 +
|fpu=Yes
 +
|x8616=Yes
 +
|x8632=Yes
 +
|x8664=Yes
 +
|nx=Yes
 +
|3dnow=No
 +
|e3dnow=No
 +
|mmx=Yes
 +
|emmx=Yes
 +
|sse=Yes
 +
|sse2=Yes
 +
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=Yes
 +
|sse42=Yes
 +
|sse4a=No
 +
|avx=No
 +
|avx2=No
 +
 +
|abm=Yes
 +
|tbm=No
 +
|bmi1=Yes
 +
|bmi2=Yes
 +
|fma3=No
 +
|fma4=No
 +
|aes=Yes
 +
|rdrand=Yes
 +
|sha=No
 +
|xop=No
 +
|adx=Yes
 +
|clmul=Yes
 +
|f16c=Yes
 +
|tbt1=No
 +
|tbt2=No
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=Yes
 +
|sst=Yes
 +
|flex=Yes
 +
|fastmem=No
 +
|isrt=Yes
 +
|sba=No
 +
|mwt=Yes
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=No
 +
|txt=No
 +
|ht=No
 +
|vpro=Yes
 +
|vtx=Yes
 +
|vtd=Yes
 +
|ept=Yes
 +
|mpx=Yes
 +
|sgx=Yes
 +
|securekey=Yes
 +
|osguard=Yes
 +
|smartmp=No
 +
|powernow=No
 +
|amdv=No
 +
|rvi=No
 
}}
 
}}

Latest revision as of 09:08, 11 February 2019

Edit Values
Celeron 3865U
General Info
DesignerIntel
ManufacturerIntel
Model Number3865U
S-SpecSR349
MarketMobile
IntroductionJanuary 3, 2017 (announced)
January 3, 2017 (launched)
ShopAmazon
General Specs
FamilyCeleron
Series3800
LockedYes
Frequency1,800 MHz
Bus typeOPI
Bus rate4 GT/s
Clock multiplier22
CPUID806E9
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureKaby Lake
PlatformKaby Lake
Core NameKaby Lake U
Core Family6
Core Model142
Core SteppingH0
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores2
Threads2
Max Memory64 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Vcore0.25 V-1.52 V
TDP15 W
cTDP down10 W
Tjunction0 °C – 100 °C
Tstorage-25 °C – 125 °C
Packaging
PackageFCBGA-1356 (BGA)
Dimension42 mm x 24 mm x 1.3 mm
Pitch0.65 mm
Ball Count1356
Ball CompSAC405
InterconnectBGA-1356

Celeron 3865U is a 64-bit dual-core budget x86 mobile microprocessors introduced by Intel in early 2017. The 3865U, which is based on the Kaby Lake microarchitecture, is fabricated on Intel's improved 14nm+ process. This processor operates at 1.8 GHz with a TDP of 15 W and supports up to 32 GiB of dual-channel non-ECC DDR4-2133. Additionally the 3865U incorporates Intel's HD Graphics 610 IGP operating at 300 MHz with a burst frequency of 900 GHz.

This model has a configurable TDP-down of 10 W.

Cache[edit]

Main article: Kaby Lake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associativewrite-back
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  2x256 KiB4-way set associativewrite-back
L3$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  2x1 MiB12-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR3-1866, DDR3L-1600, DDR4-2133
Supports ECCNo
Max Mem64 GiB
Controllers1
Channels2
Max Bandwidth31.79 GiB/s
32,552.96 MiB/s
34.134 GB/s
34,134.253 MB/s
0.031 TiB/s
0.0341 TB/s
Bandwidth
Single 15.89 GiB/s
Double 31.79 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes16
Configs1x16, 2x8, 1x8+2x4


Graphics[edit]

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUHD Graphics 610
DesignerIntelDevice ID0x5906
Execution Units12Max Displays3
Max Memory32 GiB
32,768 MiB
33,554,432 KiB
34,359,738,368 B
Frequency300 MHz
0.3 GHz
300,000 KHz
Burst Frequency900 MHz
0.9 GHz
900,000 KHz
OutputDP, eDP, HDMI, DVI
Max Resolution
HDMI4096x2304 @24 Hz
DP4096x2304 @60 Hz
eDP4096x2304 @60 Hz
Standards
DirectX12
OpenGL4.4
OpenCL2.0
DP1.2
eDP1.4
HDMI1.4a
Additional Features
Intel Quick Sync Video
Intel Clear Video
Intel Clear Video HD

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
MPXMemory Protection Extensions
SGXSoftware Guard Extensions
Secure KeySecure Key Technology
SMEPOS Guard Technology
Flex MemoryFlex Memory Access
ISRTSmart Response Technology
MWTMy WiFi Technology
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/celeron/3865u&oldid=86594"
Facts about "Celeron 3865U - Intel"
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"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Celeron 3865U - Intel#io +
device id0x5906 +
has ecc memory supportfalse +
integrated gpuHD Graphics 610 +
integrated gpu base frequency300 MHz (0.3 GHz, 300,000 KHz) +
integrated gpu designerIntel +
integrated gpu execution units12 +
integrated gpu max frequency900 MHz (0.9 GHz, 900,000 KHz) +
integrated gpu max memory32,768 MiB (33,554,432 KiB, 34,359,738,368 B, 32 GiB) +
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ description8-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description8-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description4-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ description12-way set associative +
l3$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
max memory bandwidth31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) +
max memory channels2 +
max pcie lanes16 +
supported memory typeLPDDR3-1866 +, DDR3L-1600 + and DDR4-2133 +