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Difference between revisions of "cavium/octeon plus/cn5860-800bg1521-scp"
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'''CN5860-800 SCP''' is a {{arch|64}} [[hexadeca-core]] [[MIPS]] secure communication microprocessor (SCP) designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates sixteen {{cavium|cnMIPS|l=arch}} cores, operates at 800 MHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of secure communication software such as encryption, compression/decompression, and TCP acceleration. | '''CN5860-800 SCP''' is a {{arch|64}} [[hexadeca-core]] [[MIPS]] secure communication microprocessor (SCP) designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates sixteen {{cavium|cnMIPS|l=arch}} cores, operates at 800 MHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of secure communication software such as encryption, compression/decompression, and TCP acceleration. |
Latest revision as of 15:13, 13 December 2017
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Cavium CN5860-800 SCP | |||||||
General Info | |||||||
Designer | Cavium | ||||||
Manufacturer | TSMC | ||||||
Model Number | CN5860-800 SCP | ||||||
Part Number | CN5860-800BG1521-SCP | ||||||
Market | Network | ||||||
Introduction | October 9, 2006 (announced) February, 2007 (launched) | ||||||
General Specs | |||||||
Family | OCTEON Plus | ||||||
Series | CN58xx | ||||||
Frequency | 800 MHz | ||||||
Microarchitecture | |||||||
ISA | MIPS64 (MIPS) | ||||||
Microarchitecture | cnMIPS | ||||||
Process | 90 nm | ||||||
Technology | CMOS | ||||||
Word Size | 64 bit | ||||||
Cores | 16 | ||||||
Threads | 16 | ||||||
Multiprocessing | |||||||
Max SMP | 1-Way (Uniprocessor) | ||||||
Packaging | |||||||
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CN5860-800 SCP is a 64-bit hexadeca-core MIPS secure communication microprocessor (SCP) designed by Cavium and introduced in 2007. This processor, which incorporates sixteen cnMIPS cores, operates at 800 MHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of secure communication software such as encryption, compression/decompression, and TCP acceleration.
Contents
Cache[edit]
- Main article: cnMIPS § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Expansions[edit]
Expansion Options
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Networking[edit]
Networking
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Hardware Accelerators[edit]
[Edit/Modify Accelerators Info]
Hardware Accelerators
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Block diagram[edit]
Datasheet[edit]
Facts about "CN5860-800 SCP - Cavium"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | CN5860-800 SCP - Cavium#package + |
base frequency | 800 MHz (0.8 GHz, 800,000 kHz) + |
core count | 16 + |
designer | Cavium + |
family | OCTEON Plus + |
first announced | October 9, 2006 + |
first launched | February 2007 + |
full page name | cavium/octeon plus/cn5860-800bg1521-scp + |
has ecc memory support | true + |
has hardware accelerators for cryptography | true + |
has hardware accelerators for network quality of service processing | true + |
has hardware accelerators for tcp packet processing | true + |
instance of | microprocessor + |
isa | MIPS64 + |
isa family | MIPS + |
l1$ size | 768 KiB (786,432 B, 0.75 MiB) + |
l1d$ description | 64-way set associative + |
l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1i$ description | 64-way set associative + |
l1i$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
ldate | February 2007 + |
main image | + |
manufacturer | TSMC + |
market segment | Network + |
max cpu count | 1 + |
max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + |
max memory channels | 1 + |
microarchitecture | cnMIPS + |
model number | CN5860-800 SCP + |
name | Cavium CN5860-800 SCP + |
package | FCBGA-1521 + |
part number | CN5860-800BG1521-SCP + |
process | 90 nm (0.09 μm, 9.0e-5 mm) + |
series | CN58xx + |
smp max ways | 1 + |
supported memory type | DDR2-800 + |
technology | CMOS + |
thread count | 16 + |
word size | 64 bit (8 octets, 16 nibbles) + |