Latest revision as of 15:13, 13 December 2017

Edit Values
Cavium CN5860-800 NSP
General Info
Designer	Cavium
Manufacturer	TSMC
Model Number	CN5860-800 NSP
Part Number	CN5860-800BG1521-NSP
Market	Network
Introduction	October 9, 2006 (announced) February, 2007 (launched)
General Specs
Family	OCTEON Plus
Series	CN58xx
Frequency	800 MHz
Microarchitecture
ISA	MIPS64 (MIPS)
Microarchitecture	cnMIPS
Process	90 nm
Technology	CMOS
Word Size	64 bit
Cores	16
Threads	16
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Packaging
Package FCBGA-1521 (BGA) Ball Count 1521 Interconnect BGA-1521

CN5860-800 NSP is a 64-bit hexadeca-core MIPS network service microprocessor (NSP) designed by Cavium and introduced in 2007. This processor, which incorporates sixteen cnMIPS cores, operates at 800 MHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance network services software such as encryption, RegEx, compression/decompression, and TCP acceleration.

Cache[edit]

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 768 KiB 786,432 B 0.75 MiB L1I$ 512 KiB 524,288 B 0.5 MiB 16x32 KiB 64-way set associative   L1D$ 256 KiB 262,144 B 0.25 MiB 16x16 KiB 64-way set associative   L2$ 2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB     1x2 MiB 8-way set associative

Memory controller[edit]

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR2-800 Supports ECC Yes Controllers 1 Channels 1 Width 128 bit Max Bandwidth 11.92 GiB/s 12,206.08 MiB/s 12.799 GB/s 12,799.003 MB/s 0.0116 TiB/s 0.0128 TB/s Bandwidth Single 11.92 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

	Expansion Options
	PCI-X Width 64 bit Clock 133.33 MHz Rate 1,017.25 MiB/s Features host or slave UART Ports 2 GP I/O Yes

Networking[edit]

[Edit/Modify Network Info]

	Networking
	MII RGMII Yes (Ports: 8) SPI SPI-4.2 Yes (Ports: 2)

Hardware Accelerators[edit]

[Edit/Modify Accelerators Info]

	Hardware Accelerators
	Encryption Hardware Implementation Yes Types DES, 3DES, AES-GCM, AES up to 256, SHA1, SHA-2 up to SHA-512, RSA up to 8192, DH, KASUMI RegEx RegEx Yes Features 32 Engines Networking TCP Yes QoS Yes Compression Compression Yes Decompression Yes

Block diagram[edit]

Datasheet[edit]

• OCTEON CN58XX Processors Product Brief