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| model number        = CN5850-900 EXP
 
| model number        = CN5850-900 EXP
 
| part number        = CN5850-900BG1521-EXP
 
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'''CN5850-900 EXP''' is a {{arch|64}} [[dodeca-core]] [[MIPS]] network microprocessor designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates twelve {{cavium|cnMIPS|l=arch}} cores, operates at 900 MHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of various software such as [[RegEx]], compression/decompression, and TCP acceleration.
 
'''CN5850-900 EXP''' is a {{arch|64}} [[dodeca-core]] [[MIPS]] network microprocessor designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates twelve {{cavium|cnMIPS|l=arch}} cores, operates at 900 MHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of various software such as [[RegEx]], compression/decompression, and TCP acceleration.

Latest revision as of 15:12, 13 December 2017

Edit Values
Cavium CN5850-900 EXP
octeon plus chip.png
General Info
DesignerCavium
ManufacturerTSMC
Model NumberCN5850-900 EXP
Part NumberCN5850-900BG1521-EXP
MarketNetwork
IntroductionOctober 9, 2006 (announced)
February, 2007 (launched)
General Specs
FamilyOCTEON Plus
SeriesCN58xx
Frequency900 MHz
Microarchitecture
ISAMIPS64 (MIPS)
MicroarchitecturecnMIPS
Process90 nm
TechnologyCMOS
Word Size64 bit
Cores12
Threads12
Multiprocessing
Max SMP1-Way (Uniprocessor)
Packaging
PackageFCBGA-1521 (BGA)
Ball Count1521
InterconnectBGA-1521

CN5850-900 EXP is a 64-bit dodeca-core MIPS network microprocessor designed by Cavium and introduced in 2007. This processor, which incorporates twelve cnMIPS cores, operates at 900 MHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of various software such as RegEx, compression/decompression, and TCP acceleration.


Cache[edit]

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$576 KiB
589,824 B
0.563 MiB
L1I$384 KiB
393,216 B
0.375 MiB
12x32 KiB64-way set associative 
L1D$192 KiB
196,608 B
0.188 MiB
12x16 KiB64-way set associative 
L2$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  1x2 MiB8-way set associative 

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR2-800
Supports ECCYes
Controllers1
Channels1
Width128 bit
Max Bandwidth11.92 GiB/s
12,206.08 MiB/s
12.799 GB/s
12,799.003 MB/s
0.0116 TiB/s
0.0128 TB/s
Bandwidth
Single 11.92 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCI-X
Width64 bit
Clock133.33 MHz
Rate1,017.25 MiB/s
Featureshost or slave
UART
Ports2
GP I/OYes


Networking[edit]

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
MII
RGMIIYes (Ports: 8)
SPI
SPI-4.2Yes (Ports: 2)

Hardware Accelerators[edit]

[Edit/Modify Accelerators Info]

hardware accel icon.svg
Hardware Accelerators
RegEx
RegExYes
Features32 Engines
Networking
TCPYes
QoSYes
Compression
CompressionYes
DecompressionYes

Block diagram[edit]

octeon plus cn58xx.png

Datasheet[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=cavium/octeon_plus/cn5850-900bg1521-exp&oldid=70316"
Facts about "CN5850-900 EXP - Cavium"
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Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
CN5850-900 EXP - Cavium#package +
base frequency900 MHz (0.9 GHz, 900,000 kHz) +
core count12 +
designerCavium +
familyOCTEON Plus +
first announcedOctober 9, 2006 +
first launchedFebruary 2007 +
full page namecavium/octeon plus/cn5850-900bg1521-exp +
has ecc memory supporttrue +
has hardware accelerators for data compressiontrue +
has hardware accelerators for data decompressiontrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for regular expressiontrue +
has hardware accelerators for tcp packet processingtrue +
instance ofmicroprocessor +
isaMIPS64 +
isa familyMIPS +
l1$ size576 KiB (589,824 B, 0.563 MiB) +
l1d$ description64-way set associative +
l1d$ size192 KiB (196,608 B, 0.188 MiB) +
l1i$ description64-way set associative +
l1i$ size384 KiB (393,216 B, 0.375 MiB) +
l2$ description8-way set associative +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
ldateFebruary 2007 +
main imageFile:octeon plus chip.png +
manufacturerTSMC +
market segmentNetwork +
max cpu count1 +
max memory bandwidth11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels1 +
microarchitecturecnMIPS +
model numberCN5850-900 EXP +
nameCavium CN5850-900 EXP +
packageFCBGA-1521 +
part numberCN5850-900BG1521-EXP +
process90 nm (0.09 μm, 9.0e-5 mm) +
seriesCN58xx +
smp max ways1 +
supported memory typeDDR2-800 +
technologyCMOS +
thread count12 +
word size64 bit (8 octets, 16 nibbles) +