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Difference between revisions of "cavium/octeon plus/cn5850-900bg1521-scp"
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{{cavium title|CN5850-900 SCP}}
 
{{cavium title|CN5850-900 SCP}}
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{{mpu
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{{chip
 
| name                = Cavium CN5850-900 SCP
 
| name                = Cavium CN5850-900 SCP
 
| no image            =  
 
| no image            =  
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| model number        = CN5850-900 SCP
 
| model number        = CN5850-900 SCP
 
| part number        = CN5850-900BG1521-SCP
 
| part number        = CN5850-900BG1521-SCP
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| part number 1      =
 
 
| part number 2      =  
 
| part number 2      =  
 
| part number 3      =  
 
| part number 3      =  
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| part number 4      =
 
| market              = Network
 
| market              = Network
 
| first announced    = October 9, 2006
 
| first announced    = October 9, 2006
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| core model          =  
 
| core model          =  
 
| core stepping      =  
 
| core stepping      =  
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| process            = 130 nm
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| process            = 90 nm
 
| transistors        =  
 
| transistors        =  
 
| technology          = CMOS
 
| technology          = CMOS
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| tambient max        =  
 
| tambient max        =  
  
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| packaging          = Yes
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|package module 1={{packages/cavium/fcbga-1521}}
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| package 0          = FCBGA-1521
 
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| package 0 type      = FCBGA
 
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| package 0 pins      = 1521
 
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| package 0 pitch    =  
 
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| package 0 width    =
 
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| package 0 length    =
 
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| package 0 height    =
 
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| socket 0            = BGA-1521
 
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| socket 0 type      = BGA
 
 
}}
 
}}
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'''CN5850-900 SCP''' is a {{arch|64}} [[dodeca-core]] [[MIPS]] secure communication microprocessor (SCP) designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates twelve {{cavium|cnMIPS|l=arch}} cores, operates at 900 MHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of secure communication software such as encryption, compression/decompression, and TCP acceleration.
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== Cache ==
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{{main|cavium/microarchitectures/cnmips#Memory_Hierarchy|l1=cnMIPS § Cache}}
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{{cache size
 +
|l1 cache=576 KiB
 +
|l1i cache=384 KiB
 +
|l1i break=12x32 KiB
 +
|l1i desc=64-way set associative
 +
|l1d cache=192 KiB
 +
|l1d break=12x16 KiB
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|l1d desc=64-way set associative
 +
|l2 cache=2 MiB
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|l2 break=1x2 MiB
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|l2 desc=8-way set associative
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}}
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== Memory controller ==
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{{memory controller
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|type=DDR2-800
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|ecc=Yes
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|max mem=
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|controllers=1
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|channels=1
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|width=128 bit
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|max bandwidth=11.92 GiB/s
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|bandwidth schan=11.92 GiB/s
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}}
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== Expansions ==
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{{expansions
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|pcix width=64 bit
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|pcix clock=133.33 MHz
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|pcix rate=1,017.25 MiB/s
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|pcix extra=host or slave
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|uart=yes
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|uart ports=2
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|gp io=Yes
 +
}}
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 +
== Networking ==
 +
{{network
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|mii opts=Yes
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|rgmii=yes
 +
|rgmii ports=8
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|spi opts=Yes
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|spi42=Yes
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|spi42 ports=2
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}}
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 +
== Hardware Accelerators ==
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{{accelerators
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|encryption=Yes
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|encryption type=DES, 3DES, AES-GCM, AES up to 256, SHA1, SHA-2 up to SHA-512, RSA up to 8192, DH, KASUMI
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|tcp=Yes
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|qos=Yes
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}}
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 +
== Block diagram ==
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[[File:octeon plus cn58xx.png|750px]]
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== Datasheet ==
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* [[:File:octeon plus cn58xx (rev 1.4).pdf|OCTEON CN58XX Processors Product Brief]]

Latest revision as of 15:13, 13 December 2017

Edit Values
Cavium CN5850-900 SCP
octeon plus chip.png
General Info
DesignerCavium
ManufacturerTSMC
Model NumberCN5850-900 SCP
Part NumberCN5850-900BG1521-SCP
MarketNetwork
IntroductionOctober 9, 2006 (announced)
February, 2007 (launched)
General Specs
FamilyOCTEON Plus
SeriesCN58xx
Frequency900 MHz
Microarchitecture
ISAMIPS64 (MIPS)
MicroarchitecturecnMIPS
Process90 nm
TechnologyCMOS
Word Size64 bit
Cores12
Threads12
Multiprocessing
Max SMP1-Way (Uniprocessor)
Packaging
PackageFCBGA-1521 (BGA)
Ball Count1521
InterconnectBGA-1521

CN5850-900 SCP is a 64-bit dodeca-core MIPS secure communication microprocessor (SCP) designed by Cavium and introduced in 2007. This processor, which incorporates twelve cnMIPS cores, operates at 900 MHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of secure communication software such as encryption, compression/decompression, and TCP acceleration.


Cache[edit]

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$576 KiB
589,824 B
0.563 MiB
L1I$384 KiB
393,216 B
0.375 MiB
12x32 KiB64-way set associative 
L1D$192 KiB
196,608 B
0.188 MiB
12x16 KiB64-way set associative 
L2$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  1x2 MiB8-way set associative 

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR2-800
Supports ECCYes
Controllers1
Channels1
Width128 bit
Max Bandwidth11.92 GiB/s
12,206.08 MiB/s
12.799 GB/s
12,799.003 MB/s
0.0116 TiB/s
0.0128 TB/s
Bandwidth
Single 11.92 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCI-X
Width64 bit
Clock133.33 MHz
Rate1,017.25 MiB/s
Featureshost or slave
UART
Ports2
GP I/OYes


Networking[edit]

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
MII
RGMIIYes (Ports: 8)
SPI
SPI-4.2Yes (Ports: 2)

Hardware Accelerators[edit]

[Edit/Modify Accelerators Info]

hardware accel icon.svg
Hardware Accelerators
Encryption
Hardware ImplementationYes
TypesDES, 3DES, AES-GCM, AES up to 256, SHA1, SHA-2 up to SHA-512, RSA up to 8192, DH, KASUMI
Networking
TCPYes
QoSYes

Block diagram[edit]

octeon plus cn58xx.png

Datasheet[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=cavium/octeon_plus/cn5850-900bg1521-scp&oldid=70318"
Facts about "CN5850-900 SCP - Cavium"
RDF feed
l1$ size576 KiB (589,824 B, 0.563 MiB) +
l1d$ description64-way set associative +
l1d$ size192 KiB (196,608 B, 0.188 MiB) +
l1i$ description64-way set associative +
l1i$ size384 KiB (393,216 B, 0.375 MiB) +
l2$ description8-way set associative +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +