Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "cavium/octeon/cn3850-400bg1521-exp"
m (Bot: moving all {{mpu}} to {{chip}}) |
|||
| (3 intermediate revisions by 2 users not shown) | |||
| Line 1: | Line 1: | ||
{{cavium title|CN3850-400 EXP}} | {{cavium title|CN3850-400 EXP}} | ||
| − | {{ | + | {{chip |
| name = Cavium CN3850-400 EXP | | name = Cavium CN3850-400 EXP | ||
| no image = | | no image = | ||
| Line 10: | Line 10: | ||
| model number = CN3850-400 EXP | | model number = CN3850-400 EXP | ||
| part number = CN3850-400BG1521-EXP | | part number = CN3850-400BG1521-EXP | ||
| − | |||
| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
| + | | part number 4 = | ||
| market = Networking | | market = Networking | ||
| − | | first announced = | + | | first announced = August 22, 2005 |
| − | | first launched = | + | | first launched = August 22, 2005 |
| last order = | | last order = | ||
| last shipment = | | last shipment = | ||
| Line 78: | Line 78: | ||
| tambient max = | | tambient max = | ||
| − | + | |package module 1={{packages/cavium/fcbga-1521}} | |
| − | | package | ||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
}} | }} | ||
The '''CN3850-400 EXP''' is a {{arch|64}} [[dodeca-core]] [[MIPS]] communication [[microprocessor]] designed by [[Cavium]] and introduced in [[2005]]. This processor, which incorporates twelve {{cavium|cnMIPS|l=arch}} cores, operates at 400 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory. | The '''CN3850-400 EXP''' is a {{arch|64}} [[dodeca-core]] [[MIPS]] communication [[microprocessor]] designed by [[Cavium]] and introduced in [[2005]]. This processor, which incorporates twelve {{cavium|cnMIPS|l=arch}} cores, operates at 400 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory. | ||
Latest revision as of 16:11, 13 December 2017
| Edit Values | |||||||
| Cavium CN3850-400 EXP | |||||||
 | |||||||
| General Info | |||||||
| Designer | Cavium | ||||||
| Manufacturer | TSMC | ||||||
| Model Number | CN3850-400 EXP | ||||||
| Part Number | CN3850-400BG1521-EXP | ||||||
| Market | Networking | ||||||
| Introduction | August 22, 2005 (announced) August 22, 2005 (launched) | ||||||
| General Specs | |||||||
| Family | OCTEON | ||||||
| Series | CN3800 | ||||||
| Frequency | 400 MHz | ||||||
| Microarchitecture | |||||||
| ISA | MIPS64 (MIPS) | ||||||
| Microarchitecture | cnMIPS | ||||||
| Core Name | cnMIPS | ||||||
| Process | 130 nm | ||||||
| Technology | CMOS | ||||||
| Word Size | 64 bit | ||||||
| Cores | 12 | ||||||
| Threads | 12 | ||||||
| Max Memory | 16 GiB | ||||||
| Multiprocessing | |||||||
| Max SMP | 1-Way (Uniprocessor) | ||||||
| Packaging | |||||||
| |||||||
The CN3850-400 EXP is a 64-bit dodeca-core MIPS communication microprocessor designed by Cavium and introduced in 2005. This processor, which incorporates twelve cnMIPS cores, operates at 400 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.
Contents
Cache[edit]
- Main article: cnMIPS § Cache
 |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
||||||||||||||||||||||||
|
|||||||||||||||||||||||||
Memory controller[edit]
 |
Integrated Memory Controller
|
|||||||||||||||
|
||||||||||||||||
Expansions[edit]
 |
Expansion Options
|
|||||||||||||||
|
||||||||||||||||
Networking[edit]
 |
Networking
|
|||||||
|
||||||||
Hardware Accelerators[edit]
[Edit/Modify Accelerators Info]
 |
Hardware Accelerators
|
|||||||||||||||||
|
||||||||||||||||||
Block diagram[edit]
Datasheet[edit]
Facts about "CN3850-400 EXP - Cavium"
